On Fri, 2015-08-14 at 15:55 +0300, Ville Syrjälä wrote:
> On Fri, Aug 14, 2015 at 01:03:21PM +0300, Mika Kahola wrote:
> > Store max dotclock into dev_priv structure so we are able
> > to filter out the modes that are not supported by our
> > platforms.
> >
> > V2:
> > - limit the max dot clock frequency to max CD clock frequency
> > for the gen9 and above
> > - limit the max dot clock frequency to 90% of the max CD clock
> > frequency for the older gens
> > - for Cherryview the max dot clock frequency is limited to 95%
> > of the max CD clock frequency
> > - for gen2 and gen3 the max dot clock limit is set to 90% of the
> > 2X max CD clock frequency
> >
> > V3:
> > - max_dotclk variable renamed as max_dotclk_freq in i915_drv.h
> > - in intel_compute_max_dotclk() the rounding method changed from
> > round up to round down when computing max dotclock
> >
> > Signed-off-by: Mika Kahola <mika.kahola@xxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 19 +++++++++++++++++++
> > 2 files changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 55611d8..e1910ec 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1787,6 +1787,7 @@ struct drm_i915_private {
> > unsigned int fsb_freq, mem_freq, is_ddr3;
> > unsigned int skl_boot_cdclk;
> > unsigned int cdclk_freq, max_cdclk_freq;
> > + unsigned int max_dotclk_freq;
> > unsigned int hpll_freq;
> >
> > /**
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 21aa745..e8d8860 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5275,6 +5275,20 @@ static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
> > modeset_put_power_domains(dev_priv, put_domains[i]);
> > }
> >
> > +static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > +{
> > + int max_cdclk_freq = dev_priv->max_cdclk_freq;
> > +
> > + if (INTEL_INFO(dev_priv)->gen >= 9)
>
> Sorry, I missed this the last time. The conditiona should
> actually be (HSW || BDW || gen >= 9) or something to that effect.
Allright. I add Haswell and Broadwell to this condition.
-Mika-
> Otherwise looks good, so with that fixed:
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> > + return max_cdclk_freq;
> > + else if (IS_CHERRYVIEW(dev_priv))
> > + return max_cdclk_freq*95/100;
> > + else if (INTEL_INFO(dev_priv)->gen < 4)
> > + return 2*max_cdclk_freq*90/100;
> > + else
> > + return max_cdclk_freq*90/100;
> > +}
> > +
> > static void intel_update_max_cdclk(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -5314,8 +5328,13 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> > dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
> > }
> >
> > + dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
> > +
> > DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
> > dev_priv->max_cdclk_freq);
> > +
> > + DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
> > + dev_priv->max_dotclk_freq);
> > }
> >
> > static void intel_update_cdclk(struct drm_device *dev)
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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