On Wed, Aug 12, 2015 at 07:04:22PM +0300, Ville Syrjälä wrote: > On Mon, Jul 06, 2015 at 03:09:59PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > While working on CHV DPIO powergating I relized DP .compute_config() was > > clobbering lane_count etc. stored in intel_dp. This could cause problems > > if we do the .compute_config() but later fail the modeset for some reason. > > Any subsequent link re-training might then fail if intel_dp->lane_count > > etc. got changed. > > > > The reason I ran into this during the DPIO powergating work was that I may > > need to know which lanes he active when shutting down the link. However > > .compute_config() already clobbered that information by the time I need it. > > By moving it to the pipe config we avoid that problem as well. > > > > I also cleaned up the limited color range handling a bit while I was > > in the neighborhood. > > > > > drm/i915: Clean up DP/HDMI limited color range handling > > drm/i915: Move intel_dp->lane_count into pipe_config > > These two are still lacking a r-b. Would be nice to get these in so that > they don't end up blocking the CHV DPIO powergating stuff once that gets > reviewed. > > Sivakumar, any chance you'd like to review those as well? Or do we have > anyone else interested? All merged to dinq, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
