From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
While working on CHV DPIO powergating I relized DP .compute_config() was
clobbering lane_count etc. stored in intel_dp. This could cause problems
if we do the .compute_config() but later fail the modeset for some reason.
Any subsequent link re-training might then fail if intel_dp->lane_count
etc. got changed.
The reason I ran into this during the DPIO powergating work was that I may
need to know which lanes he active when shutting down the link. However
.compute_config() already clobbered that information by the time I need it.
By moving it to the pipe config we avoid that problem as well.
I also cleaned up the limited color range handling a bit while I was
in the neighborhood.
Ville Syrjälä (7):
drm/i915: Clean up DP/HDMI limited color range handling
drm/i915: Don't use link_bw for PLL setup
drm/i915: Don't pass clock to DDI PLL select functions
drm/i915: Avoid confusion between DP and TRANS_DP_CTL in DP
.get_config()
drm/i915: Move intel_dp->lane_count into pipe_config
drm/i915: Don't use link_bw to select between TP1 and TP3
drm/i915: Kill intel_dp->{link_bw,rate_select}
drivers/gpu/drm/i915/i915_reg.h | 3 +
drivers/gpu/drm/i915/intel_ddi.c | 41 ++++----
drivers/gpu/drm/i915/intel_display.c | 7 +-
drivers/gpu/drm/i915/intel_dp.c | 177 ++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_dp_mst.c | 19 ++--
drivers/gpu/drm/i915/intel_drv.h | 9 +-
drivers/gpu/drm/i915/intel_hdmi.c | 26 +++--
7 files changed, 155 insertions(+), 127 deletions(-)
--
2.3.6
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