On 7/30/2015 5:01 AM, Goel, Akash wrote:
On 7/29/2015 9:53 PM, Michel Thierry wrote:Introduces the Page Map Level 4 (PML4), ie. the new top level structure of the page tables. To facilitate testing, 48b mode will be available on Broadwell and GEN9+, when i915.enable_ppgtt = 3. v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt code is already 32/64-bit safe (Chris). v3: Add goto free_scratch in temp 48-bit mode init code (Akash). Cc: Akash Goel <akash.goel@xxxxxxxxx> Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> @@ -557,6 +563,8 @@ static void free_pdp(struct drm_device *dev, struct i915_page_directory_pointer *pdp) { __pdp_fini(pdp); + if (USES_FULL_48BIT_PPGTT(dev)) + kfree(pdp);Sorry for the late comment. This change is a bit of distraction here, should be moved to the following 'alloc/free for 4lvl' patch. Best regards Akash
kfree(pdp) moved to patch 7/19. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
