From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
While trawling the w/a database I spotted a workaround we didn't
have related to CHV DPLL pixel multiuplier setting. So I set forth
to implement it, and while doing that I ended up cleaning up the
VLV/CHV DPLL handling a bit. This also touched the DSI code a bit
and while testing that I noticed some problems with out DSI PLL
handling so I included a fix for those.
Ville Syrjälä (9):
drm/i915: Keep GMCH DPLL VGA mode always disabled
drm/i915: Apply OCD to VLV/CHV DPLL defines
drm/i915: Simplify CHV pipe A power well code
drm/i915: Refactor VLV display power well init/deinit
drm/i915: Clear out DPLL state from pipe config in DSI get config
drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well
enable
drm/i915: Make {vlv,chv}_{disable,update}_pll() more similar
drm/i915: Implement WaPixelRepeatModeFixForC0:chv
drm/i915: Disable DSI PLL before reconfiguring it
drivers/gpu/drm/i915/i915_drv.h | 7 ++
drivers/gpu/drm/i915/i915_reg.h | 9 ++-
drivers/gpu/drm/i915/intel_display.c | 99 +++++++++++++++-------------
drivers/gpu/drm/i915/intel_dsi.c | 16 ++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 110 +++++++++++++++-----------------
5 files changed, 124 insertions(+), 117 deletions(-)
--
2.3.6
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