On Fri, May 22, 2015 at 11:22:31AM +0300, Mika Kahola wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Actually read the HPLLCC register insted of assuming it's 0. Fix the
> HPLLCC bit definitions and all the missing ones from the 852GME spec.
>
> 852GME, 854 and 855 all seem to match the same HPLLC encoding even
> though only some of the values are valid is some of the platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> v2: Rebased to the latest
> v3: Rebased to the latest
>
> Reviewed-by: Mika Kahola <mika.kahola@xxxxxxxxx>
>
> Author: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
-ENODOC
Acked -by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++---
> drivers/gpu/drm/i915/intel_display.c | 15 ++++++++++++---
> 2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 84af255..6625fb3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -50,12 +50,17 @@
>
> /* PCI config space */
>
> -#define HPLLCC 0xc0 /* 855 only */
> -#define GC_CLOCK_CONTROL_MASK (0xf << 0)
> +#define HPLLCC 0xc0 /* 85x only */
> +#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
> #define GC_CLOCK_133_200 (0 << 0)
> #define GC_CLOCK_100_200 (1 << 0)
> #define GC_CLOCK_100_133 (2 << 0)
> -#define GC_CLOCK_166_250 (3 << 0)
> +#define GC_CLOCK_133_266 (3 << 0)
> +#define GC_CLOCK_133_200_2 (4 << 0)
> +#define GC_CLOCK_133_266_2 (5 << 0)
> +#define GC_CLOCK_166_266 (6 << 0)
> +#define GC_CLOCK_166_250 (7 << 0)
> +
> #define GCFGC2 0xda
> #define GCFGC 0xf0 /* 915+ only */
> #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c97b496..64debfb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6627,20 +6627,29 @@ static int i865_get_display_clock_speed(struct drm_device *dev)
> return 266667;
> }
>
> -static int i855_get_display_clock_speed(struct drm_device *dev)
> +static int i85x_get_display_clock_speed(struct drm_device *dev)
> {
> u16 hpllcc = 0;
> +
> + pci_bus_read_config_word(dev->pdev->bus,
> + PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
> +
> /* Assume that the hardware is in the high speed state. This
> * should be the default.
> */
> switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
> case GC_CLOCK_133_200:
> + case GC_CLOCK_133_200_2:
> case GC_CLOCK_100_200:
> return 200000;
> case GC_CLOCK_166_250:
> return 250000;
> case GC_CLOCK_100_133:
> return 133333;
> + case GC_CLOCK_133_266:
> + case GC_CLOCK_133_266_2:
> + case GC_CLOCK_166_266:
> + return 266667;
> }
>
> /* Shouldn't happen */
> @@ -14199,8 +14208,8 @@ static void intel_init_display(struct drm_device *dev)
> i865_get_display_clock_speed;
> else if (IS_I85X(dev))
> dev_priv->display.get_display_clock_speed =
> - i855_get_display_clock_speed;
> - else /* 852, 830 */
> + i85x_get_display_clock_speed;
> + else /* 830 */
> dev_priv->display.get_display_clock_speed =
> i830_get_display_clock_speed;
>
> --
> 1.9.1
>
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