On Wednesday, May 06, 2015 08:25:28 PM Mika Kuoppala wrote: > Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > > > On Wed, May 06, 2015 at 03:38:44PM +0200, Daniel Vetter wrote: > >> On Tue, Apr 21, 2015 at 10:13:31PM -0700, Kenneth Graunke wrote: > >> > The BLT engine on Gen8+ requires linear surfaces to be cacheline > >> > aligned. This restriction was added as part of converting the BLT to > >> > use 48-bit addressing. > >> > > >> > intel_emit_linear_blit needs to handle blits that are not cacheline > >> > aligned, as we use it for arbitrary glBufferSubData calls and subrange > >> > mappings. > >> > > >> > Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst > >> > pixel X offset field to represent the unaligned portion, and subtract > >> > that from the address so it's cacheline aligned. > >> > > >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521 > >> > Signed-off-by: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> > >> > Cc: mesa-stable@xxxxxxxxxxxxxxxxxxxxx > >> > >> s/cacheline/page/ afaik, and nope it's not documented. Chris&Mika learned > >> that the hard way. Adding them to correct me in case I make a mess again. > > > > It's cacheline. > > > > Issue: if the 1st pixel in XY_SRC_COPY is not CL aligned when SRC or > > DST are linear that will cause failure. > > > > https://vthsd.fm.intel.com/hsd/bdwgfx/bug_de/default.aspx?bug_de_id=1912704 > > -Chris > > > > FWIF, I ended up doing it like this in igt: > > http://lists.freedesktop.org/archives/intel-gfx/2015-January/059191.html > > And I think the documentation was updated on the restrictions. > > -Mika Yeah, I saw the updated documentation, remembered that Chris warned me about this a while back (I think I just said "ugh" and promptly forgot about it), and finally fixed Mesa. It's all upstream and working now. Huge thanks for tracking this down and getting it documented!
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