On Fri, 10 Apr 2015, Imre Deak <imre.deak@xxxxxxxxx> wrote:
> From: Shashank Sharma <shashank.sharma@xxxxxxxxx>
>
> This patch adds conditional checks in gen8_irq functions
> to support BXT. Most of the checks just look for PCH split
> availability, and block the call to PCH interrupt functions if
> not available.
>
> v2: (jani)
> - drop redundant TODO comment about PCH IRQ flags on BXT
> - check HAS_PCH_SPLIT instead of IS_BROXTON when handling PCH specific
> IRQ events in gen8_irq_handler()
> - check HAS_PCH_SPLIT before calling the function instead of a
> corresponding early return within the called function for
> ibx_irq_reset(), ibx_irq_pre_postinstall(), ibx_irq_postinstall()
>
> Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@xxxxxxxxx>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> Signed-off-by: Shashank Sharma <ppashank.sharma@xxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 21 ++++++++++++++-------
> 1 file changed, 14 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b06364f..a185f44 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2297,7 +2297,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
> DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
> }
>
> - if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
> + if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
> + master_ctl & GEN8_DE_PCH_IRQ) {
> /*
> * FIXME(BDW): Assume for now that the new interrupt handling
> * scheme also closed the SDE interrupt handling race we've seen
> @@ -3073,7 +3074,8 @@ static void ironlake_irq_reset(struct drm_device *dev)
>
> gen5_gt_irq_reset(dev);
>
> - ibx_irq_reset(dev);
> + if (HAS_PCH_SPLIT(dev))
> + ibx_irq_reset(dev);
> }
>
> static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3133,7 +3135,8 @@ static void gen8_irq_reset(struct drm_device *dev)
> GEN5_IRQ_RESET(GEN8_DE_MISC_);
> GEN5_IRQ_RESET(GEN8_PCU_);
>
> - ibx_irq_reset(dev);
> + if (HAS_PCH_SPLIT(dev))
> + ibx_irq_reset(dev);
> }
>
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -3323,13 +3326,15 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>
> I915_WRITE(HWSTAM, 0xeffe);
>
> - ibx_irq_pre_postinstall(dev);
> + if (HAS_PCH_SPLIT(dev))
> + ibx_irq_pre_postinstall(dev);
>
> GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
>
> gen5_gt_irq_postinstall(dev);
>
> - ibx_irq_postinstall(dev);
> + if (HAS_PCH_SPLIT(dev))
> + ibx_irq_postinstall(dev);
/me scratches head, we shouldn't ever call ironlake_irq_postinstall on
bxt, should we? Did I miss something?
With this hunk dropped, I think the patch looks good.
BR,
Jani.
>
> if (IS_IRONLAKE_M(dev)) {
> /* Enable PCU event interrupts
> @@ -3545,12 +3550,14 @@ static int gen8_irq_postinstall(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - ibx_irq_pre_postinstall(dev);
> + if (HAS_PCH_SPLIT(dev))
> + ibx_irq_pre_postinstall(dev);
>
> gen8_gt_irq_postinstall(dev_priv);
> gen8_de_irq_postinstall(dev_priv);
>
> - ibx_irq_postinstall(dev);
> + if (HAS_PCH_SPLIT(dev))
> + ibx_irq_postinstall(dev);
>
> I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
> POSTING_READ(GEN8_MASTER_IRQ);
> --
> 1.9.1
>
--
Jani Nikula, Intel Open Source Technology Center
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