Helper function updates supported scaling ratios based on cdclk and
crtc clocks.
v2:
-update single copy of scaling ratios (Matt)
v3:
-min scaling ratio is limited by either display engine limit or clocks,
it is not related to previous ratio (Matt, me)
Signed-off-by: Chandra Konduru <chandra.konduru@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ec58f1d..29d46fc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4513,6 +4513,31 @@ static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
intel_wait_for_vblank(dev, other_active_crtc->pipe);
}
+static void skl_update_scaling_ratio(struct drm_device *dev,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t crtc_clock, cdclk;
+ struct intel_crtc_scaler_state *scaler_state;
+
+ if (!crtc_state)
+ return;
+
+ crtc_clock = (uint32_t) crtc_state->base.adjusted_mode.crtc_clock;
+ cdclk = (uint32_t) intel_ddi_get_cdclk_freq(dev_priv);
+
+ if (!crtc_clock || !cdclk)
+ return;
+
+ scaler_state = &crtc_state->scaler_state;
+ scaler_state->min_hsr = max((uint32_t)34, (crtc_clock * 100)/cdclk);
+ scaler_state->min_vsr = max((uint32_t)34, (crtc_clock * 100)/cdclk);
+ scaler_state->min_hvsr = max((uint32_t)12, (crtc_clock * 100)/cdclk);
+
+ DRM_DEBUG_KMS("for crtc_state = %p crtc_clock = %d cdclk = %d\n", crtc_state,
+ crtc_clock, cdclk);
+}
+
static void haswell_crtc_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
--
1.7.9.5
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