On 03/17/2015 02:40 AM, Imre Deak wrote:
> From: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx>
>
> Add placeholder function for calculating programmed pixel clock.
> Note: Formula to back calculate link clock from dividers not
> available currently.
>
> v2:
> - rebased on upstream s/crtc_config/crtc_state/ change (imre)
>
> Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@xxxxxxxxx> (v1)
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 30 +++++++++++++++++++++++++++++-
> drivers/gpu/drm/i915/intel_dp.c | 2 ++
> 2 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0a5d71e..ff62054 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -851,6 +851,32 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
> pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
> }
>
> +static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
> + enum intel_dpll_id dpll)
> +{
> + /* FIXME formula not available in bspec */
> + return 0;
> +}
> +
> +static void bxt_ddi_clock_get(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> + enum port port = intel_ddi_get_encoder_port(encoder);
> + uint32_t dpll = port;
> +
> + pipe_config->port_clock =
> + bxt_calc_pll_link(dev_priv, dpll);
> +
> + if (pipe_config->has_dp_encoder)
> + pipe_config->base.adjusted_mode.crtc_clock =
> + intel_dotclock_calculate(pipe_config->port_clock,
> + &pipe_config->dp_m_n);
> + else
> + pipe_config->base.adjusted_mode.crtc_clock =
> + pipe_config->port_clock;
> +}
> +
> void intel_ddi_clock_get(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> {
> @@ -858,8 +884,10 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>
> if (INTEL_INFO(dev)->gen <= 8)
> hsw_ddi_clock_get(encoder, pipe_config);
> - else
> + else if (IS_SKYLAKE(dev))
> skl_ddi_clock_get(encoder, pipe_config);
> + else if (IS_BROXTON(dev))
> + bxt_ddi_clock_get(encoder, pipe_config);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index ca60060..4bfbeed 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1416,6 +1416,8 @@ found:
>
> if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
> + else if (IS_BROXTON(dev))
> + /* handled in ddi */;
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
> else
>
Another one for JIRA. Looks like the formulas are in there now:
Actual Output = M2 * 400 / (P1 * P2) // Actual differs from desired due
to limited M2 fractional precision
Reviewed-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
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