On Wed, Mar 11, 2015 at 06:58:12PM +0200, Ville Syrjälä wrote: > On Wed, Mar 11, 2015 at 11:37:54AM +0000, Conselvan De Oliveira, Ander wrote: > > On Wed, 2015-03-11 at 13:35 +0200, Ander Conselvan de Oliveira wrote: > > > Remove the global modeset resource function that would disable the > > > bifurcation bit, and instead enable/disable it when enabling the pch > > > transcoder. The mode set consistency check should prevent us from > > > disabling the bit if pipe C is enabled so the change should be safe. > > > > > > Note that this doens't affect the logic that prevents the bit being > > > set while a pipe is active, since the patch retains the behavior of > > > only chaging the bit if necessary. Because of the checks during mode > > > set, the first change would necessarily happen with both pipes B and > > > C disabled, and any subsequent write would be skipped. > > > > > > v2: Only change the bit during pch trancoder enable. (Ville) > > > > Oops, I forgot the sob line. > > > > Signed-off-by: Ander Conselvan de Oliveira > > <ander.conselvan.de.oliveira@xxxxxxxxx> > > > So I was staring at this stuff for a while and I believe it should be > fine. We don't keep the bifurcation state entirely consistent when > neither of the the pipes B/C are actually driving a PCH transcoder, but > that shouldn't really matter. If we want to make it consistent then I > suggest that we go with my earlier idea of only changing the state at > transcoder B with >2 lanes enable/disable, and otherwise keep it enabled > all the time. The slight complication there is the initial state we get > from the BIOS which might not match that, so we'd need to sanitize it > or something. > > Anyway, I also posted a couple of patches on top that try to sort out > ironlake_check_fdi_lanes() [1]. With those and this one I think things > should work even better than before. > > So for this patch: > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Queued for -next, thanks for the patch. -Daniel >-- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
