Re: [v2 5/5] drm/i915: Update prop, int co-eff and gain threshold for CHV

["Purushothaman, Vijay A" <vijay.a.purushothaman@xxxxxxxxxxxxxxx>]

On 2/16/2015 5:02 PM, Ville Syrjälä wrote:
> On Mon, Feb 16, 2015 at 03:08:02PM +0530, Vijay Purushothaman wrote:
> > This patch implements latest PHY changes in Gain, prop and int co-efficients
> > based on the vco freq.
> >
> > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@xxxxxxxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h      |    1 +
> >   drivers/gpu/drm/i915/intel_display.c |   42 ++++++++++++++++++++++++----------
> >   2 files changed, 31 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 5814f67..b5bce4e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1027,6 +1027,7 @@ enum skl_disp_power_wells {
> >   
> >   #define _CHV_PLL_DW8_CH0		0x8020
> >   #define _CHV_PLL_DW8_CH1		0x81A0
> > +#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> >   #define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
> >   
> >   #define _CHV_PLL_DW9_CH0		0x8024
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ae2a77f..ca02cf7 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6039,10 +6039,10 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> >   	int pipe = crtc->pipe;
> >   	int dpll_reg = DPLL(crtc->pipe);
> >   	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> > -	u32 loopfilter, intcoeff;
> > +	u32 loopfilter, tribuf_calcntr;
> >   	u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
> >   	u32 dpio_val;
> > -	int refclk;
> > +	int vco;
> >   
> >   	bestn = pipe_config->dpll.n;
> >   	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
> > @@ -6050,7 +6050,9 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> >   	bestm2 = pipe_config->dpll.m2 >> 22;
> >   	bestp1 = pipe_config->dpll.p1;
> >   	bestp2 = pipe_config->dpll.p2;
> > +	vco = pipe_config->dpll.vco;
> >   	dpio_val = 0;
> > +	loopfilter = 0;
> >   
> >   	/*
> >   	 * Enable Refclk and SSC
> > @@ -6104,18 +6106,34 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> >   	}
> >   
> >   	/* Loop filter */
> > -	refclk = i9xx_get_refclk(crtc, 0);
> > -	loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
> > -		2 << DPIO_CHV_GAIN_CTRL_SHIFT;
> > -	if (refclk == 100000)
> > -		intcoeff = 11;
> > -	else if (refclk == 38400)
> > -		intcoeff = 10;
> > -	else
> > -		intcoeff = 9;
> > -	loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
> > +	if (vco == 5400000) {
> > +		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
> > +		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
> > +		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
> > +		tribuf_calcntr = 0;
> In your original patch tribuf_calcntr was 9 here. Which is correct?
9 is correct. Thanks for the catch.
> > +	} else if (vco <= 6200000) {
> > +		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
> > +		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
> > +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> > +		tribuf_calcntr = 0x9;
> > +	} else if (vco <= 6480000) {
> > +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> > +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> > +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> > +		tribuf_calcntr = 0x8;
> > +	} else {
> > +		/* Not supported. Apply the same limits as in the max case */
> > +		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
> > +		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
> > +		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
> These too were different in your original patch, but I guess it doens't
> matter either way that much since we should never get here.
Correct. Just for clarity, i wanted to use the max limits.

Thanks,
Vijay
> > +		tribuf_calcntr = 0;
> > +	}
> >   	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
> >   
> > +	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
> > +	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> Need to clear out the old bits again. Seems to be 10bits by the looks of it.
>
> > +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
> > +
> >   	/* AFC Recal */
> >   	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
> >   			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> > --
> > 1.7.9.5
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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