On Fri, Feb 20, 2015 at 05:45:54PM +0000, Michel Thierry wrote: > These patches rely on "PPGTT dynamic page allocations", currently under review, > to provide GEN8 dynamic page table support with 64b addresses. As the review > progresses, these patches may be combined. > > In order expand the GPU address space, a 4th level translation is added, the > Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255], > each pointing to a PDP. > > For now, this feature will only be available in BDW, in LRC submission mode > (execlists) and when i915.enable_ppgtt=3 is set. > Also note that this expanded address space is only available for full PPGTT, > aliasing PPGTT remains 32b. FWIW, I don't think it sounds like a good idea to enable 48bits address spaces without having implemented Wa32bitGeneralStateOffset and Wa32bitInstructionBaseOffset. -- Damien _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
