On Fri, Feb 20, 2015 at 05:45:54PM +0000, Michel Thierry wrote: > These patches rely on "PPGTT dynamic page allocations", currently under review, > to provide GEN8 dynamic page table support with 64b addresses. As the review > progresses, these patches may be combined. > > In order expand the GPU address space, a 4th level translation is added, the > Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255], > each pointing to a PDP. > > For now, this feature will only be available in BDW, in LRC submission mode > (execlists) and when i915.enable_ppgtt=3 is set. > Also note that this expanded address space is only available for full PPGTT, > aliasing PPGTT remains 32b. Any reasons for restricting this to bdw and not just going with gen9+ right away? We could just merge it and then fix fallout or selective revert when it blows up on chv/skl - those platforms aren't shipping yet, so regressions aren't too onerous. -Daniel > > Ben Widawsky (9): > drm/i915/bdw: Make pdp allocation more dynamic > drm/i915/bdw: Abstract PDP usage > drm/i915/bdw: Add dynamic page trace events > drm/i915/bdw: Add ppgtt info for dynamic pages > drm/i915/bdw: implement alloc/free for 4lvl > drm/i915/bdw: Add 4 level switching infrastructure > drm/i915/bdw: Generalize PTE writing for GEN8 PPGTT > drm/i915: Plumb sg_iter through va allocation ->maps > drm/i915: Expand error state's address width to 64b > > Michel Thierry (3): > drm/i915/bdw: Support 64 bit PPGTT in lrc mode > drm/i915/bdw: Add 4 level support in insert_entries and clear_range > drm/i915/bdw: Flip the 48b switch > > drivers/gpu/drm/i915/i915_debugfs.c | 19 +- > drivers/gpu/drm/i915/i915_drv.h | 11 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 624 ++++++++++++++++++++++++++++------ > drivers/gpu/drm/i915/i915_gem_gtt.h | 77 ++++- > drivers/gpu/drm/i915/i915_gpu_error.c | 17 +- > drivers/gpu/drm/i915/i915_params.c | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/i915_trace.h | 16 + > drivers/gpu/drm/i915/intel_lrc.c | 167 ++++++--- > 9 files changed, 746 insertions(+), 188 deletions(-) > > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
