Very appreciate. :) Thanks Thomas! -----Original Message----- From: Daniel, Thomas Sent: Tuesday, February 10, 2015 10:56 PM To: Wang, Zhi A; Intel-gfx@xxxxxxxxxxxxxxxxxxxxx Subject: RE: About CTX_CONTEXT_CONTROL initialization in populate_lr_context() intel_lrc.c > -----Original Message----- > From: Wang, Zhi A > Sent: Tuesday, February 10, 2015 2:44 PM > To: Daniel, Thomas; Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Subject: RE: About CTX_CONTEXT_CONTROL initialization in > populate_lr_context() intel_lrc.c > > Hi Thomas: > Thanks for the information! Learned a lot. :) > > I remember that semaphore is disabled on Gen8 for a long time ago. > Recently I found it has been enabled. just thought that if a workload > which isn't being protected by MI_ARB_ON_OFF may be switched out by > failing to wait semaphore here without that bit? Please check i915_drv.c i915_semaphore_is_enabled - should return false if execlists are enabled, or if we are on Gen8. > Would you mind to give a help to confirm the correct combos? That > would be nice and great helpful to me :) > > a. Set "Inhibit Synchronous Context Switch" bit, HW will wait until > the condition is true or specific event is generated if SW issue some > instructions like MI_SEMAPHORE_WAIT, I thought that's why SW don't > need to process CSB with wait_semaphore bit set. But if MI_ARB_ON_OFF > is ON, Can SW do a preemption here by submitting a new ELSP write combo? Correct. However the driver will never cause a pre-emption in this way at the moment. > b. Clear "Inhibit Synchronous Context Switch", HW will switch out > context directly after the condition is false or specific event is not > generated at that time, and write a CSB with wait_semaphore bit is > set. And SW has to be aware this kinds of CSB in this case I think... Correct. But as I said, I don't think any of these events will be generated. Thomas. _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
