On Mon, Nov 17, 2014 at 07:46:08PM +0100, Daniel Vetter wrote: > On Mon, Nov 17, 2014 at 04:43:40PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > We don't currently have cdclk extraction code for 965g,snb,ivb. > > Let's assumee 400 MHz until we know better. That seems to match hints > > in various vague documents. Whether that's good enough is not > > entirely clear. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Hm, not sure whether these chips even had outputs which could drive this > high really. And if we now start rejecting modes that previously worked > (really unlikely imo) we'll get the regression reports and can fudge the > numbers some more. So even without more spec hints I'm totally fine with > going forward with this. At least one IVB out there seems to agree with this 400MHz limit: https://bugs.freedesktop.org/show_bug.cgi?id=85621 But it does look like we're also failing to respect the port limits which according to BSpec are 315Mhz-388Mhz (depending on the port and/or bpc) for IVB. So I guess you're right that the cdclk wouldn't matter all that much if we actually checked the port limits. Although there are also various sprite scaling/format related limits we fail to check where the limit ends up being of the form cdclk*N where N is something < 1.0. So having a decent approximation of the cdclk around should be useful eventually. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
