On Fri, Nov 14, 2014 at 05:24:35PM +0000, Damien Lespiau wrote: > Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index b5a279a..924f1ec 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -767,12 +767,20 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder, > > pipe_config->port_clock = link_clock; > > + /* > + * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part of the > + * shared DPLL framework and thus needs to be read out separately > + */ > + if (encoder->type == INTEL_OUTPUT_EDP) Hw state readout shouldn't depend upon our sw state, and given the multiple personality nature of DDI ports I think this is the case here: We might have a different opinion than the bios guys about what's edp (it happened) or how consistently to apply this clock selection algo (also happened). So might be better to stuff this into the ddi clock readout code (the one where you patched away the WARN for DPLL0 I guess). Merged patch 3 meanwhile, thanks. -Daniel > + pipe_config->dpll_hw_state.ctrl1 = (dpll_ctl1 >> (dpll * 6)) & 0x3f; > + > if (pipe_config->has_dp_encoder) > pipe_config->adjusted_mode.crtc_clock = > intel_dotclock_calculate(pipe_config->port_clock, > &pipe_config->dp_m_n); > else > pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; > + > } > > static void hsw_ddi_clock_get(struct intel_encoder *encoder, > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
