The previous clock series didn't include the eDP side of it. This should
address most of it, for now.
Note that I have some issues with HBR2 and link training here and I'm trying to
find more information about this. So depending on the configuration (number of
lanes wired, panel bw) this series may not be enough to light up an eDP panel.
--
Damien
Damien Lespiau (4):
drm/i915/skl: Remove spurious warn in get_ddi_pll()
drm/i915/skl: Set the eDP link rate on DPLL0
drm/i915/skl: Use the pipe config DPLL tracking to query the link
clock
drm/i915/skl: Read out crtl1 for eDP/DPLL0
drivers/gpu/drm/i915/intel_ddi.c | 34 +++++++++++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_display.c | 2 --
drivers/gpu/drm/i915/intel_dp.c | 31 ++++++++++++++++++++++++++++++-
3 files changed, 59 insertions(+), 8 deletions(-)
--
1.8.3.1
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