2014-11-14 15:24 GMT-02:00 Damien Lespiau <damien.lespiau@xxxxxxxxx>: > The previous clock series didn't include the eDP side of it. This should > address most of it, for now. > > Note that I have some issues with HBR2 and link training here and I'm trying to > find more information about this. So depending on the configuration (number of > lanes wired, panel bw) this series may not be enough to light up an eDP panel. I couldn't spot anything obvious here... For all patches: Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> My bikeshedding would be to replace the magic "(id * 6)" - from patches 2 and 4 - and "0x3f" - from patch 4 - with some nice macro definitions. > > -- > Damien > > Damien Lespiau (4): > drm/i915/skl: Remove spurious warn in get_ddi_pll() > drm/i915/skl: Set the eDP link rate on DPLL0 > drm/i915/skl: Use the pipe config DPLL tracking to query the link > clock > drm/i915/skl: Read out crtl1 for eDP/DPLL0 > > drivers/gpu/drm/i915/intel_ddi.c | 34 +++++++++++++++++++++++++++++----- > drivers/gpu/drm/i915/intel_display.c | 2 -- > drivers/gpu/drm/i915/intel_dp.c | 31 ++++++++++++++++++++++++++++++- > 3 files changed, 59 insertions(+), 8 deletions(-) > > -- > 1.8.3.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
