On Wed, Nov 12, 2014 at 04:57:10PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Currently it's possible to get visible cache dirt on scanout on LLC > machines when using pwrite on the future scanout bo if its cache_level > is already NONE. > > pwrite's "does this need clflush?" checks would decide that no clflush > is necessary since the bo isn't currently pinned to the display and LLC > makes everything else coherent. The subsequent set_cache_level(NONE) > would also do nothing since cache_level is already correct. And hence > no clflush will be performed and we flip to a bo which can still have > dirty data in the caches. > > To correctly track the cache dirtyness move the object to CPU write > domain in pwrite. This cures the cache dirt since we explicitly flush > the CPU write domain in the pin_to_display path. > > Give pread the same treatment simply in the name of symmetry. > > v2: Use trace_i915_gem_object_change_domain() and provide some kind > of commit message > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Also usual drill: Can I haz testcase pls? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
