On Wed, Nov 12, 2014 at 03:01:30PM +0000, Chris Wilson wrote: > On Wed, Nov 12, 2014 at 04:57:10PM +0200, ville.syrjala@xxxxxxxxxxxxxxx wrote: > > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > > > Currently it's possible to get visible cache dirt on scanout on LLC > > machines when using pwrite on the future scanout bo if its cache_level > > is already NONE. > > > > pwrite's "does this need clflush?" checks would decide that no clflush > > is necessary since the bo isn't currently pinned to the display and LLC > > makes everything else coherent. The subsequent set_cache_level(NONE) > > would also do nothing since cache_level is already correct. And hence > > no clflush will be performed and we flip to a bo which can still have > > dirty data in the caches. > > > > To correctly track the cache dirtyness move the object to CPU write > > domain in pwrite. This cures the cache dirt since we explicitly flush > > the CPU write domain in the pin_to_display path. > > > > Give pread the same treatment simply in the name of symmetry. > > > > v2: Use trace_i915_gem_object_change_domain() and provide some kind > > of commit message > > > > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > --- > > v1 was floated on irc. > > Doesn't it still suffer the same problem that only accessed cache lines > are clflushed, but we declare the entire object as valid? Ah in case there's already dirty stuff in the cache before the pwrite? Hmm, yeah that would be a problem. How about about clearing write_domain in the end only if write_domain was != CPU in the start? -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
