From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Updated gen6|8_enable_rps() for Haswell and Broadwell
to use the efficient frequency read from pcode.
Added hsw_use_efficient_freq() to read efficient
frequency (aka RPe) from pcode. The efficiency is
based on the frequency/power ratio (MHz/W); this is
considering GT power and not package power. The
efficent frequency is the highest frequency for which
the frequency/power ratio is within some threshold of
the highest frequency/power ratio.
Also set the min_freq_softlimit to the efficient
frequency. A fixed decrease in frequency results in
smaller decrease in power at frequencies less than RPe
than at frequencies above RPe.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d43fa0e..6fbfdec 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6010,6 +6010,7 @@ enum punit_power_well {
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
#define DISPLAY_IPS_CONTROL 0x19
+#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA 0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 300d7e5..e4347d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4706,6 +4706,18 @@ static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_c
dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
}
+static void hsw_use_efficient_freq(struct drm_i915_private *dev_priv)
+{
+ u32 ddcc_status = 0;
+ int ret;
+
+ ret = sandybridge_pcode_read(dev_priv,
+ HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ &ddcc_status);
+ if (0 == ret)
+ dev_priv->rps.efficient_freq = (ddcc_status >> 8) & 0xff;
+}
+
static void gen9_enable_rps(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4765,6 +4777,11 @@ static void gen8_enable_rps(struct drm_device *dev)
rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
parse_rp_state_cap(dev_priv, rp_state_cap);
+ if (IS_BROADWELL(dev)) {
+ hsw_use_efficient_freq(dev_priv);
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq;
+ }
+
/* 2b: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4860,6 +4877,11 @@ static void gen6_enable_rps(struct drm_device *dev)
parse_rp_state_cap(dev_priv, rp_state_cap);
+ if (IS_HASWELL(dev)) {
+ hsw_use_efficient_freq(dev_priv);
+ dev_priv->rps.min_freq_softlimit = dev_priv->rps.efficient_freq;
+ }
+
/* disable the counters and set deterministic thresholds */
I915_WRITE(GEN6_RC_CONTROL, 0);
--
1.7.9.5
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