On Tue, Nov 04, 2014 at 05:06:38PM +0000, Damien Lespiau wrote:
> From: Pradeep Bhat <pradeep.bhat@xxxxxxxxx>
>
> This patch reads the memory latency values for all the 8 levels for
> SKL. These values are needed for the Watermark computation.
>
> v2: Incorporated the review comments from Damien on register
> indentation.
>
> v3: Updated the code to use the sandybridge_pcode_read for reading
> memory latencies for GEN9.
>
> v4: Don't put gen 9 in the middle of an ordered list of ifs
> (Damien)
>
> v5: take the rps.hw_lock around sandybridge_pcode_read() (Damien)
>
> v6: Use gen >= 9 in the pcode_read() function for data1.
> Move the defines near the gen6 ones and prefix them with PCODE.
> Remove unused timeout define (the pcode_read() code has a larger
> timeout already).
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Pradeep Bhat <pradeep.bhat@xxxxxxxxx>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++
> drivers/gpu/drm/i915/i915_reg.h | 7 ++++
> drivers/gpu/drm/i915/intel_pm.c | 76 +++++++++++++++++++++++++++++++++++++----
> 3 files changed, 83 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 54691bc..05fcbe5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1678,6 +1678,12 @@ struct drm_i915_private {
> uint16_t spr_latency[5];
> /* cursor */
> uint16_t cur_latency[5];
> + /*
> + * Raw watermark memory latency values
> + * for SKL for all 8 levels
> + * in 1us units.
> + */
> + uint16_t skl_latency[8];
>
> /* current hardware state */
> struct ilk_wm_values hw;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f32c624..3f469c8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5957,6 +5957,13 @@ enum punit_power_well {
> #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
> #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
>
> +#define GEN9_PCODE_DATA1 0x13812C
> +#define GEN9_PCODE_READ_MEM_LATENCY 0x6
> +#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
> +#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
> +#define GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT 16
> +#define GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT 24
> +
> #define GEN6_GT_CORE_STATUS 0x138060
> #define GEN6_CORE_CPD_STATE_MASK (7<<4)
> #define GEN6_RCn_MASK 7
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a69eba..761c884 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2271,11 +2271,56 @@ hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
> PIPE_WM_LINETIME_TIME(linetime);
> }
>
> -static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
> +static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
Imo we should split this into an ilk_read_wm_latency and a
skl_read_wm_latency function. It's big and all the callers seem to only
care about one or the other. Care for a follow-up patch?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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