On Mon, Nov 03, 2014 at 02:51:27PM +0100, Daniel Vetter wrote: > On Wed, Oct 29, 2014 at 11:32:33AM +0200, Ander Conselvan de Oliveira wrote: > > It is possible for a mode set to fail if there aren't shared DPLLS that > > match the new configuration requirement or other errors in clock > > computation. If that step is executed after disabling crtcs, in the > > failure case the hardware configuration is changed and needs to be > > restored. Doing those things early will allow the mode set to fail > > before actually touching the hardware. > > > > Follow up patches will convert different platforms to use the new > > infrastructure. > > > > v2: Keep pll->new_config valid only during mode set (Ville) > > Use kmemdup() in i915_shared_dpll_start_config() (Ville) > > Restore old pll config if something fails before commit (Ville) > > Don't set compute_clock hooks since dev_priv is kzalloc()'d (Ville) > > > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@xxxxxxxxx> > > Ran into a blocking question with this one, merged thus far. > > > @@ -7395,6 +7456,9 @@ static int ironlake_crtc_mode_set(struct intel_crtc *crtc, > > else > > crtc->new_config->dpll_hw_state.fp1 = fp; > > > > + if (intel_crtc_to_shared_dpll(crtc)) > > + intel_put_shared_dpll(crtc); > > Don't we need the same fixup in intel_ddi_pll_select? Ok, I think I've figured it out - hsw does an unconditional put since a ddi pll might not be needed (for e.g. DP). -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
