On Mon, Oct 27, 2014 at 09:48:27AM +0100, Daniel Vetter wrote:
> On Tue, Oct 07, 2014 at 05:41:21PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > We need to access the gunit mailbox when changing the cdclk frequency.
> > Currently we update the power wells only after chancing cdclk, so the
> > device might be suspended when we have to frob it. Grab a runtime PM
> > reference to make sure it's awake.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Late response because mailman.
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index d83a7f1..149310b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4812,10 +4812,12 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> > int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
> >
> > if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> > + intel_runtime_pm_get(dev_priv);
> > if (IS_CHERRYVIEW(dev))
> > cherryview_set_cdclk(dev, req_cdclk);
> > else
> > valleyview_set_cdclk(dev, req_cdclk);
> > + intel_runtime_pm_put(dev_priv);
>
> So shouldn't we move the cdclock within modeset_update_crtc_power_domains?
> That one first grabs new domains then drops old ones to make sure we don't
> ever touch the hw in the off state.
Yeah that would be a nicer solution, or maybe split
modeset_update_crtc_power_domains() into pre and post funcs?
There was also a patch somewhere in the list that frobbed with some
PFI credits or somesuch depending on the cdclk frequency, and I believe
that may require the disp2d power well since the register could live
there. So this rpm ref solution might not be enough in the end.
>
> Also vlv noob question: Does the cdclock setting survive a runtime suspend
> transition, i.e. when we'd routine suspend right here between the cdclock
> change and grabbing power wells (e.g. when turning everything on).
I would expect it does survive since it's just a register value we write
into punit/cck. But I'm not entirely sure what would happen on VLV if
we choose 400MHz cdclk and then the entire soc enters s0ix. In that case
I could imagine that Punit would reissue the cdclk request to cck on
resume, which would then cause cdclk to come back as 320/333 MHz instead
of the 400MHz we were expecting. That too is just a theory at this
point.
> -Daniel
>
> > }
> >
> > modeset_update_crtc_power_domains(dev);
> > --
> > 2.0.4
> >
> > _______________________________________________
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> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
--
Ville Syrjälä
Intel OTC
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