On Tue, Oct 07, 2014 at 05:41:21PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> We need to access the gunit mailbox when changing the cdclk frequency.
> Currently we update the power wells only after chancing cdclk, so the
> device might be suspended when we have to frob it. Grab a runtime PM
> reference to make sure it's awake.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Late response because mailman.
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d83a7f1..149310b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4812,10 +4812,12 @@ static void valleyview_modeset_global_resources(struct drm_device *dev)
> int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
>
> if (req_cdclk != dev_priv->vlv_cdclk_freq) {
> + intel_runtime_pm_get(dev_priv);
> if (IS_CHERRYVIEW(dev))
> cherryview_set_cdclk(dev, req_cdclk);
> else
> valleyview_set_cdclk(dev, req_cdclk);
> + intel_runtime_pm_put(dev_priv);
So shouldn't we move the cdclock within modeset_update_crtc_power_domains?
That one first grabs new domains then drops old ones to make sure we don't
ever touch the hw in the off state.
Also vlv noob question: Does the cdclock setting survive a runtime suspend
transition, i.e. when we'd routine suspend right here between the cdclock
change and grabbing power wells (e.g. when turning everything on).
-Daniel
> }
>
> modeset_update_crtc_power_domains(dev);
> --
> 2.0.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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