On Thu, Sep 25, 2014 at 09:26:36AM -0700, clinton.a.taylor@xxxxxxxxx wrote:
> From: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
>
> HDMI audio clock config was incorrectly choosing the default for
> pixel doubled interlaced modes. The table was missing pixel clock
> values 13.500 (27.000) and 13.513 (27.027). Luckily the default N
> value for 25.200 is the same N value for both 27MHz pixel clocks,
> a warning message was being printed with drm.debug set.
>
> ver2: Use 13500 * 1001 / 1000 instead of 13513 constant.
>
> Cc: Jani Nikula <jani.nikula at intel.com>
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 858011d..e76a4106 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7872,6 +7872,8 @@ static struct {
> { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
> { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
> { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
> + { 13500, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
> + { 13500 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
We have double clocked modes where the non-doubled clock is already
27MHz so this seems like a bandaid for one particular case rather than a
full solution.
The HDMI specification makes it clear that the N/CTS stuff depends on
the TMDS clock and not the pixel clock, but BSpec just talks about pixel
clock without further explaining any of this stuff. So should we look
at port_clock rather than the pixel clock here?
> };
>
> /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
> --
> 1.7.9.5
>
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--
Ville Syrjälä
Intel OTC
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