On Wed, Sep 24, 2014 at 03:49:39PM -0700, clinton.a.taylor@xxxxxxxxx wrote:
> From: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
>
> port_clock was being incorrectly computed and WRPLL was incorrectly
> programmed for pixel doubled modes using a 27.027MHz pixel clock.
> port_clock was set to 27.026 resulting in an output pixel clock
> matching 27.000MHz.
I don't understand how this 27.000MHz clock would come about. Can you
explain further?
> Since there is no way to correctly half the 27.027
> frequency as an integer just set port_clock to 27027 for these modes.
>
> Signed-off-by: Clint Taylor <clinton.a.taylor@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 29ec153..a0786d6 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -933,6 +933,11 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
> pipe_config->pixel_multiplier = 2;
> +
> + /* Fix up port_clock since 27027 is not divisible by 2 */
> + if (pipe_config->adjusted_mode.crtc_clock == 13513) {
> + pipe_config->port_clock = 27027;
> + }
Ugh. Oh well I suppose we'll want to be as accurate as possible. Would
be nice if would could someone do this fixup already in drm core, but
that would probably require changing to smaller clock units all over
the place which doesn't sound fun at all. So I guess we get to leave
the kludge in the driver :(
This also got me thinking about the 12bpc case as well. It's clearly
busted with double clocked modes now. Care to fix that up as well?
PS. did you ever send that separate patch to fix up the interlace
flags in some of the double clocked modes? I don't remember seeing
such a patch at least.
> }
>
> if (intel_hdmi->color_range)
> --
> 1.7.9.5
>
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--
Ville Syrjälä
Intel OTC
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