On Fri, Sep 19, 2014 at 08:49:06PM +0300, Ville Syrjälä wrote: > On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote: > > as these have been fixed in production hw and hurt performance > > if applied. > > > > v2: adjust requested ring space (Ville) > > > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 > > Tested-by: zhoujian <jianx.zhou@xxxxxxxxx> > > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > > Documentation agrees that these can go. > Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Cc: stable@xxxxxxxxxxxxxxx imo. Jani? -Daniel > > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++------------- > > 1 file changed, 2 insertions(+), 13 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index 681ea86..679a3c7 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > > * update the number of dwords required based on the > > * actual number of workarounds applied > > */ > > - ret = intel_ring_begin(ring, 24); > > + ret = intel_ring_begin(ring, 18); > > if (ret) > > return ret; > > > > @@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) > > intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, > > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > > > > - /* > > - * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for > > - * pre-production hardware > > - */ > > intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, > > - _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS > > - | GEN8_SAMPLER_POWER_BYPASS_DIS)); > > - > > - intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1, > > - _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > - > > - intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2, > > - _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); > > + _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); > > > > /* Use Force Non-Coherent whenever executing a 3D context. This is a > > * workaround for for a possible hang in the unlikely event a TLB > > -- > > 1.9.1 > > -- > Ville Syrjälä > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
