On Wed, Aug 13, 2014 at 11:51:54AM +0100, Chris Wilson wrote:
> As we use WC updates of the PTE, we are responsible for notifying the
> hardware when to flush its TLBs. Do so after we zap all the PTEs before
> suspend (and the BIOS tries to read our GTT).
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Imo would make more sense to add them to the clear_range functions.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +++++++++++++-
> 2 files changed, 14 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d1513e6ea50d..d0222cb9b7a5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2082,7 +2082,7 @@ struct drm_i915_cmd_table {
>
> /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
> #define __I915__(p) ((sizeof(*(p)) == sizeof(struct drm_i915_private)) ? \
> - (struct drm_i915_private *)(p) : to_i915(p))
> + (struct drm_i915_private *)(p) : to_i915((struct drm_device *)p))
> #define INTEL_INFO(p) (&__I915__(p)->info)
> #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index f3fd448505f1..b8d5a5d67a73 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1316,6 +1316,16 @@ void i915_check_and_clear_faults(struct drm_device *dev)
> POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
> }
>
> +static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
> +{
> + if (INTEL_INFO(dev_priv)->gen < 6) {
> + intel_gtt_chipset_flush();
> + } else {
> + I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
> + POSTING_READ(GFX_FLSH_CNTL_GEN6);
> + }
> +}
> +
> void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -1332,6 +1342,8 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
> dev_priv->gtt.base.start,
> dev_priv->gtt.base.total,
> true);
> +
> + i915_ggtt_flush(dev_priv);
> }
>
> void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> @@ -1384,7 +1396,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
> }
>
> - i915_gem_chipset_flush(dev);
> + i915_ggtt_flush(dev_priv);
> }
>
> int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
> --
> 2.1.0.rc1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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