Adding relevant mailing lists. On Fri, Aug 8, 2014 at 1:23 PM, Juergen Gross <jgross@xxxxxxxx> wrote: > I'm just about to create a patch for full PAT support in the Linux > kernel, including Xen. For this purpose I introduce a translation > between cache modes and pte bits. > > Scanning the kernel sources for usage of the cache mode bits in the > pte I discovered drivers/gpu/drm/i915/i915_gem_gtt.h is using > _PAGE_PCD, _PAGE_PWT and _PAGE_PAT. I think those defines are used > to create ptes not for usage by the main processor, but for the > graphics processor. Is this true? In this case I'd suggest to define > i915-specific macros instead of using the x86 ones. Yeah, those are gpu specific PAT tables, but the hw engineers specifically designed this to match, and we've tried to follow the cpu side to match it. Especially in the future that will be somewhat important, since we want to fully share the entire address space between cpu and gpu on the next platform. Jesse is working on that. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
