On Tue, Aug 05, 2014 at 11:15:54PM +0530, Gajanan Bhat wrote: > Round up clock computation and limit drain latency to maximum of 0x7F. > > Signed-off-by: Gajanan Bhat <gajanan.bhat@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ea64675..5e81c49 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1285,11 +1285,14 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc, > if (WARN(pixel_size == 0, "Pixel size is zero!\n")) > return false; > > - entries = (clock / 1000) * pixel_size; > + entries = DIV_ROUND_UP(clock, 1000) * pixel_size; > *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : > DRAIN_LATENCY_PRECISION_32; > *drain_latency = (64 * (*prec_mult) * 4) / entries; > > + if (*drain_latency > DRAIN_LATENCY_MASK) > + *drain_latency = DRAIN_LATENCY_MASK; I would have probably written this as: *drain_latency = min(..., DRAIN_LATENCY_MASK); But that's just a style I like. The patch looks fine to me so: Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > + > return true; > } > > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
