On Mon, Aug 04, 2014 at 11:15:16AM -0700, Rodrigo Vivi wrote:
> From: Ben Widawsky <benjamin.widawsky@xxxxxxxxx>
>
> We do this already for previous GENs. I guess we must do it for BDW too
> according to DOCS.
>
> "Pipe_control with CS-stall bit set must be issued before a
> pipe-control command that has the State Cache Invalidate bit set."
>
> This does not solve the problem I have unfortunately.
>
> I didn't check if this was in Ville's CHV series. If it was, I
> apologize.
Ken's version from long ago was included there. It's just waiting
to be merged.
>
> NOTE: I tried to use smaller lengths for the command, but nothing made
> it happy except 6.
>
> Cc: Kenneth Graunke <kenneth@xxxxxxxxxxxxx>
> Cc: Jordan Justen <jljusten@xxxxxxxxx>
> Signed-off-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9a562b5..2e566e0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -279,17 +279,25 @@ gen6_render_ring_flush(struct intel_engine_cs *ring,
> static int
> gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
> {
> - int ret;
> + int ret, size = 4;
>
> - ret = intel_ring_begin(ring, 4);
> + if (IS_BROADWELL(ring->dev))
> + size += 2;
> +
> + ret = intel_ring_begin(ring, size);
> if (ret)
> return ret;
>
> - intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
> + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(size));
> intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_STALL_AT_SCOREBOARD);
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, 0);
> + if (IS_BROADWELL(ring->dev)) {
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> + }
> +
> intel_ring_advance(ring);
>
> return 0;
> @@ -422,6 +430,11 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
> flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_QW_WRITE;
> flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
> +
> + /* Workaround: we must issue a pipe_control with CS-stall bit
> + * set before a pipe_control command that has the state cache
> + * invalidate bit set. */
> + gen7_render_ring_cs_stall_wa(ring);
> }
>
> return gen8_emit_pipe_control(ring, flags, scratch_addr);
> --
> 1.9.3
>
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--
Ville Syrjälä
Intel OTC
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