On Fri, Jul 18, 2014 at 02:04:56PM +0100, Damien Lespiau wrote: > On Fri, Jul 18, 2014 at 04:53:34PM +0530, Jindal, Sonika wrote: > > > > > > On 7/18/2014 4:26 PM, Damien Lespiau wrote: > > >On Fri, Jul 18, 2014 at 11:04:03AM +0530, sonika.jindal@xxxxxxxxx wrote: > > >>From: Sonika Jindal <sonika.jindal@xxxxxxxxx> > > >> > > >>This series prepares future platform enabling by changing HAS_PCH_SPLIT to more > > >>appropriate check since the code accessed may not have anything to do with > > >>having PCH or not. > > > > > >Hi Sonika, > > > > > >HAS_PCH_SPLIT() is true for Ironlake (gen 5) as it's paired with the > > >Ibex Peak PCH. > > > > > >In various patches, the condition needs to be INTEL_INFO(dev)->gen < 5 > > >then. > > > > > I am sorry, my understanding was that HAS_PCH_SPLIT is equivalent to > > (gen > 5 && !(IS_VALLEYVIEW) ) > > So, is it like, HAS_PCH_SPLIT is equivalent to (gen >=5 && !(IS_VALEYVIEW)) > > Yes, indeed! Since the patches need to be respun anyway, I vote for the introduction of HAS_GMCH_DISPLAY for the gen < 5 || IS_VLV condition. Since vlv (i.e. byt + chv) have essentially inherited the gmch display block from gen3/4. I think that would help the readability of the code quite a bit. Comments? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
