Re: [PATCH 3/7] drm/i915: keep freq/opcode conversion function more generic

[Deepak S <deepak.s@xxxxxxxxxxxxxxx>]

On Wednesday 09 July 2014 05:33 PM, Daniel Vetter wrote:
> On Thu, Jul 10, 2014 at 01:16:23PM +0530, deepak.s@xxxxxxxxxxxxxxx wrote:
> > From: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> >
> > Since freq/encode conversion formula changes from platform to platform,
> > create a generic wrapper function and having platform check inside this
> > help to simpilfy adding newer platform freq/opcode conversion.
> >
> > Signed-off-by: Deepak S <deepak.s@xxxxxxxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++-----
> >   drivers/gpu/drm/i915/i915_drv.h     |  4 +--
> >   drivers/gpu/drm/i915/i915_sysfs.c   | 18 ++++++-------
> >   drivers/gpu/drm/i915/intel_pm.c     | 52 +++++++++++++++++++++++++++----------
> >   4 files changed, 56 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index b3b56c4..dd7078d 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1140,14 +1140,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> >   
> >   		val = valleyview_rps_max_freq(dev_priv);
> >   		seq_printf(m, "max GPU freq: %d MHz\n",
> > -			   vlv_gpu_freq(dev_priv, val));
> > +			   intel_gpu_freq(dev_priv, val));
> intel_ is a bit too generic a prefix for a function which seems to be only
> used on byt+chv. I'd just add a if (IS_CHERRYVIEW) ... else /* vlv code */
> to both functions and not extract further.
>
> Aside: Since marketing stopped using vlv and switched to byt we're using
> vlv for code shared by byt and chv and byt_ for byt-only code. Helps a bit
> to keep things appart.
> -Daniel

Ok. Will it be Ok to use "vlv_gpu_freq" and have BYT and CHV check under this function?

The reason why i made more generic is it will help us to add conversion logic for future platforms

Thanks
Deepak


> >   
> >   		val = valleyview_rps_min_freq(dev_priv);
> >   		seq_printf(m, "min GPU freq: %d MHz\n",
> > -			   vlv_gpu_freq(dev_priv, val));
> > +			   intel_gpu_freq(dev_priv, val));
> >   
> >   		seq_printf(m, "current GPU freq: %d MHz\n",
> > -			   vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> > +			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
> >   		mutex_unlock(&dev_priv->rps.hw_lock);
> >   	} else {
> >   		seq_puts(m, "no P-state info available\n");
> > @@ -3667,7 +3667,7 @@ i915_max_freq_get(void *data, u64 *val)
> >   		return ret;
> >   
> >   	if (IS_VALLEYVIEW(dev))
> > -		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> > +		*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> >   	else
> >   		*val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
> >   	mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -3698,7 +3698,7 @@ i915_max_freq_set(void *data, u64 val)
> >   	 * Turbo will still be enabled, but won't go above the set value.
> >   	 */
> >   	if (IS_VALLEYVIEW(dev)) {
> > -		val = vlv_freq_opcode(dev_priv, val);
> > +		val = intel_freq_opcode(dev_priv, val);
> >   
> >   		hw_max = valleyview_rps_max_freq(dev_priv);
> >   		hw_min = valleyview_rps_min_freq(dev_priv);
> > @@ -3748,7 +3748,7 @@ i915_min_freq_get(void *data, u64 *val)
> >   		return ret;
> >   
> >   	if (IS_VALLEYVIEW(dev))
> > -		*val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> > +		*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> >   	else
> >   		*val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
> >   	mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -3779,7 +3779,7 @@ i915_min_freq_set(void *data, u64 val)
> >   	 * Turbo will still be enabled, but won't go below the set value.
> >   	 */
> >   	if (IS_VALLEYVIEW(dev)) {
> > -		val = vlv_freq_opcode(dev_priv, val);
> > +		val = intel_freq_opcode(dev_priv, val);
> >   
> >   		hw_max = valleyview_rps_max_freq(dev_priv);
> >   		hw_min = valleyview_rps_min_freq(dev_priv);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 90216bb..bce4654 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2749,8 +2749,8 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> >   u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> >   void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> >   
> > -int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
> > -int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
> > +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
> > +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
> >   
> >   #define FORCEWAKE_RENDER	(1 << 0)
> >   #define FORCEWAKE_MEDIA		(1 << 1)
> > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> > index b15c8ce..adfc4b9 100644
> > --- a/drivers/gpu/drm/i915/i915_sysfs.c
> > +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> > @@ -269,7 +269,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
> >   	if (IS_VALLEYVIEW(dev_priv->dev)) {
> >   		u32 freq;
> >   		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> > -		ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> > +		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> >   	} else {
> >   		ret = dev_priv->rps.cur_freq * GT_FREQUENCY_MULTIPLIER;
> >   	}
> > @@ -288,7 +288,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> >   
> >   	return snprintf(buf, PAGE_SIZE, "%d\n",
> > -			vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> > +			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
> >   }
> >   
> >   static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
> > @@ -302,7 +302,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
> >   
> >   	mutex_lock(&dev_priv->rps.hw_lock);
> >   	if (IS_VALLEYVIEW(dev_priv->dev))
> > -		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> > +		ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
> >   	else
> >   		ret = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
> >   	mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -329,7 +329,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
> >   	mutex_lock(&dev_priv->rps.hw_lock);
> >   
> >   	if (IS_VALLEYVIEW(dev_priv->dev))
> > -		val = vlv_freq_opcode(dev_priv, val);
> > +		val = intel_freq_opcode(dev_priv, val);
> >   	else
> >   		val /= GT_FREQUENCY_MULTIPLIER;
> >   
> > @@ -374,7 +374,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
> >   
> >   	mutex_lock(&dev_priv->rps.hw_lock);
> >   	if (IS_VALLEYVIEW(dev_priv->dev))
> > -		ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> > +		ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
> >   	else
> >   		ret = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
> >   	mutex_unlock(&dev_priv->rps.hw_lock);
> > @@ -401,7 +401,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
> >   	mutex_lock(&dev_priv->rps.hw_lock);
> >   
> >   	if (IS_VALLEYVIEW(dev))
> > -		val = vlv_freq_opcode(dev_priv, val);
> > +		val = intel_freq_opcode(dev_priv, val);
> >   	else
> >   		val /= GT_FREQUENCY_MULTIPLIER;
> >   
> > @@ -462,17 +462,17 @@ static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr
> >   
> >   	if (attr == &dev_attr_gt_RP0_freq_mhz) {
> >   		if (IS_VALLEYVIEW(dev))
> > -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
> > +			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);
> >   		else
> >   			val = ((rp_state_cap & 0x0000ff) >> 0) * GT_FREQUENCY_MULTIPLIER;
> >   	} else if (attr == &dev_attr_gt_RP1_freq_mhz) {
> >   		if (IS_VALLEYVIEW(dev))
> > -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
> > +			val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);
> >   		else
> >   			val = ((rp_state_cap & 0x00ff00) >> 8) * GT_FREQUENCY_MULTIPLIER;
> >   	} else if (attr == &dev_attr_gt_RPn_freq_mhz) {
> >   		if (IS_VALLEYVIEW(dev))
> > -			val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq);
> > +			val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);
> >   		else
> >   			val = ((rp_state_cap & 0xff0000) >> 16) * GT_FREQUENCY_MULTIPLIER;
> >   	} else {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index b8e7afc..9dfebab 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3328,9 +3328,9 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
> >   	WARN_ON(val < dev_priv->rps.min_freq_softlimit);
> >   
> >   	DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> >   			 dev_priv->rps.cur_freq,
> > -			 vlv_gpu_freq(dev_priv, val), val);
> > +			 intel_gpu_freq(dev_priv, val), val);
> >   
> >   	if (val != dev_priv->rps.cur_freq)
> >   		vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
> > @@ -3338,7 +3338,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
> >   	I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
> >   
> >   	dev_priv->rps.cur_freq = val;
> > -	trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
> > +	trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
> >   }
> >   
> >   static void gen8_disable_rps_interrupts(struct drm_device *dev)
> > @@ -3961,22 +3961,22 @@ static void valleyview_init_gt_powersave(struct drm_device *dev)
> >   	dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
> >   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> >   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> >   			 dev_priv->rps.max_freq);
> >   
> >   	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
> >   	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> >   			 dev_priv->rps.efficient_freq);
> >   
> >   	dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
> >   	DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
> >   			 dev_priv->rps.rp1_freq);
> >   
> >   	dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
> >   	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> >   			 dev_priv->rps.min_freq);
> >   
> >   	/* Preserve min/max settings in case of re-init */
> > @@ -4000,17 +4000,17 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
> >   	dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
> >   	dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
> >   	DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
> >   			 dev_priv->rps.max_freq);
> >   
> >   	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
> >   	DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> >   			 dev_priv->rps.efficient_freq);
> >   
> >   	dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv);
> >   	DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
> >   			 dev_priv->rps.min_freq);
> >   
> >   	/* Preserve min/max settings in case of re-init */
> > @@ -4106,11 +4106,11 @@ static void cherryview_enable_rps(struct drm_device *dev)
> >   
> >   	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> >   	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> >   			 dev_priv->rps.cur_freq);
> >   
> >   	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> >   			 dev_priv->rps.efficient_freq);
> >   
> >   	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> > @@ -4184,11 +4184,11 @@ static void valleyview_enable_rps(struct drm_device *dev)
> >   
> >   	dev_priv->rps.cur_freq = (val >> 8) & 0xff;
> >   	DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
> >   			 dev_priv->rps.cur_freq);
> >   
> >   	DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
> > -			 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> > +			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
> >   			 dev_priv->rps.efficient_freq);
> >   
> >   	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
> > @@ -6946,6 +6946,30 @@ int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
> >   	return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
> >   }
> >   
> > +int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
> > +{
> > +	int ret;
> > +
> > +	if (!IS_VALLEYVIEW(dev_priv->dev))
> > +		return -1;
> > +
> > +	ret = vlv_gpu_freq(dev_priv, val);
> > +
> > +	return ret;
> > +}
> > +
> > +int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
> > +{
> > +	int ret;
> > +
> > +	if (!IS_VALLEYVIEW(dev_priv->dev))
> > +		return -1;
> > +
> > +	ret = vlv_freq_opcode(dev_priv, val);
> > +
> > +	return ret;
> > +}
> > +
> >   void intel_pm_setup(struct drm_device *dev)
> >   {
> >   	struct drm_i915_private *dev_priv = dev->dev_private;
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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