michel.thierry@xxxxxxxxx writes: > From: Michel Thierry <michel.thierry@xxxxxxxxx> > > The workaround to limit SDE poly depth FIFO to 2 is not applied because > 3D Chicken-3 mask bit is not set. > > WaLimitSizeOfSDEPolyFifo is only for BDW-A and could be removed. > > Signed-off-by: Michel Thierry <michel.thierry@xxxxxxxxx> Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 31ae2b4..ae68df6 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5360,7 +5360,7 @@ static void gen8_init_clock_gating(struct drm_device *dev) > I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); > > I915_WRITE(_3D_CHICKEN3, > - _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); > + _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); > > I915_WRITE(COMMON_SLICE_CHICKEN2, > _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); > -- > 1.9.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
