On Mon, Jun 16, 2014 at 11:32:39AM +0300, Ville Syrjälä wrote:
> On Sun, Jun 15, 2014 at 02:55:42PM +0200, Daniel Vetter wrote:
> > It changes at runtime and so should be ignored for pipe state checks.
> > Note that we don't yet read out the full DRRS state, so there's some
> > gaps. Bu DRRS is also not yet enabled for LVDS by default.
> >
> > Cc: Aleks <aleks@xxxxxxxxxxxxxxxxxxxxxx>
> > Reported-by: Aleks <aleks@xxxxxxxxxxxxxxxxxxxxxx>
> > Cc: stable@xxxxxxxxxxxxxxx
> > Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ba1d9aac3958..1ccf660e67d9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8549,6 +8549,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> > else
> > fp = pipe_config->dpll_hw_state.fp1;
> >
> > + /* We don't compute the FPA 0/1 selector. */
> > + dpll &= ~DISPLAY_RATE_SELECT_FPA1;
> > +
>
> But we still compute port_clock based on the currently active FPA
> register. Won't that make the clock checks fail as well?
Well yeah, but that should get solved as part of the DRRS stuff I think.
Imo ignore the frequency selector for the dpll state is the right thing.
DRRS with state readout is still in-flux and unsolved wrt fastbooting.
Should I add a caveat to the commit message that this isn't everything or
not worth it as-is?
-Daniel
>
> > clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
> > if (IS_PINEVIEW(dev)) {
> > clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
> > --
> > 2.0.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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