It changes at runtime and so should be ignored for pipe state checks.
Note that we don't yet read out the full DRRS state, so there's some
gaps. Bu DRRS is also not yet enabled for LVDS by default.
Cc: Aleks <aleks@xxxxxxxxxxxxxxxxxxxxxx>
Reported-by: Aleks <aleks@xxxxxxxxxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ba1d9aac3958..1ccf660e67d9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8549,6 +8549,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
else
fp = pipe_config->dpll_hw_state.fp1;
+ /* We don't compute the FPA 0/1 selector. */
+ dpll &= ~DISPLAY_RATE_SELECT_FPA1;
+
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
if (IS_PINEVIEW(dev)) {
clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
--
2.0.0
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