On Tue, Jun 10, 2014 at 12:29:20AM +0200, Thomas Richter wrote: > Hi Ville, > > thanks for the latest patch. As said, the screen did not come back quite > correctly. I checked the register values > again, and I am sorry to say that I was wrong - register values do > differ. Apparently, the code configures now > the wrong pipe to generate output to the DVO and thus the DVO does not > seem to synchronize correctly > anymore. Please find the two register dumps attached. Either pipe can drive DVO just fine. Looks like it's using pipe A in your register dump, and all the registers look fine to me. Well, DPLL B VCO enable is off since we don't currently have a mechanism to kick pipe B into action during resume/load. In theory that would need to be enabled as well. Can you see if a simple 'intel_reg_write 0x6018 0xc08b0000' fixes the problem? And if not, I'd like to see a diff of register dumps between working and non working setups. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
