Hi Ville,thanks for the latest patch. As said, the screen did not come back quite correctly. I checked the register values again, and I am sorry to say that I was wrong - register values do differ. Apparently, the code configures now the wrong pipe to generate output to the DVO and thus the DVO does not seem to synchronize correctly
anymore. Please find the two register dumps attached. Greetings, Thomas
Attachment:
reg.org
Description: Binary data
DCC: 0x00000000 (`7v·ô??¿bFx·ä??¿ô?r·Ø??¿d?y·) CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present) C0DRB0: 0x00000000 (0x0000) C0DRB1: 0x00000000 (0x0000) C0DRB2: 0x00000000 (0x0000) C0DRB3: 0x00000000 (0x0000) C1DRB0: 0x00000000 (0x0000) C1DRB1: 0x00000000 (0x0000) C1DRB2: 0x00000000 (0x0000) C1DRB3: 0x00000000 (0x0000) C0DRA01: 0x00000000 (0x0000) C0DRA23: 0x00000000 (0x0000) C1DRA01: 0x00000000 (0x0000) C1DRA23: 0x00000000 (0x0000) PGETBL_CTL: 0x3ff60001 VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) CACHE_MODE_0: 0x001f0000 D_STATE: 0x00000000 DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT) RENCLK_GATE_D1: 0x00000000 RENCLK_GATE_D2: 0x00000000 SDVOB: 0x90004084 (enabled, pipe A, stall disabled, detected) SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected) SDVOUDI: 0x00000000 DSPARB: 0x00017e5f DSPFW1: 0x00000000 DSPFW2: 0x00000000 DSPFW3: 0x00000000 ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync) LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) DVOB: 0x90004084 (enabled, pipe A, stall, -hsync, -vsync) DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) DVOA_SRCDIM: 0x00000000 DVOB_SRCDIM: 0x00000000 DVOC_SRCDIM: 0x00000000 PP_CONTROL: 0x00000000 (power target: off) PP_STATUS: 0x00000000 (off, not ready, sequencing idle) PP_ON_DELAYS: 0x00000000 PP_OFF_DELAYS: 0x00000000 PP_DIVISOR: 0x00000000 PFIT_CONTROL: 0x00000000 PFIT_PGM_RATIOS: 0x00000000 PORT_HOTPLUG_EN: 0x00000000 PORT_HOTPLUG_STAT: 0x00000000 DSPACNTR: 0xd8000000 (enabled, pipe A) DSPASTRIDE: 0x00002000 (8192 bytes) DSPAPOS: 0x00000000 (0, 0) DSPASIZE: 0x02ff03ff (1024, 768) DSPABASE: 0x02000000 DSPASURF: 0x00000000 DSPATILEOFF: 0x00000000 PIPEACONF: 0x80000000 (enabled, single-wide) PIPEASRC: 0x03ff02ff (1024, 768) PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) PIPEA_GMCH_DATA_M: 0x00000000 PIPEA_GMCH_DATA_N: 0x00000000 PIPEA_DP_LINK_M: 0x00000000 PIPEA_DP_LINK_N: 0x00000000 CURSOR_A_BASE: 0x3524c000 CURSOR_A_CONTROL: 0x04000027 CURSOR_A_POSITION: 0x00d50133 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13) FPA1: 0x0004150d (n = 4, m1 = 21, m2 = 13) DPLL_A: 0xd0820000 (enabled, dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) DPLL_A_MD: 0x00000000 HTOTAL_A: 0x053f03ff (1024 active, 1344 total) HBLANK_A: 0x053f03ff (1024 start, 1344 end) HSYNC_A: 0x049f0417 (1048 start, 1184 end) VTOTAL_A: 0x032502ff (768 active, 806 total) VBLANK_A: 0x032502ff (768 start, 806 end) VSYNC_A: 0x03080302 (771 start, 777 end) BCLRPAT_A: 0x00000000 VSYNCSHIFT_A: 0x00000000 DSPBCNTR: 0x00000000 (disabled, pipe A) DSPBSTRIDE: 0x00000000 (0 bytes) DSPBPOS: 0x00000000 (0, 0) DSPBSIZE: 0x00000000 (1, 1) DSPBBASE: 0x00000000 DSPBSURF: 0x00000000 DSPBTILEOFF: 0x00000000 PIPEBCONF: 0x00000000 (disabled, single-wide) PIPEBSRC: 0x00000000 (1, 1) PIPEBSTAT: 0x10000004 (status: CRC_DONE_ENABLE SVBLANK_INT_STATUS) PIPEB_GMCH_DATA_M: 0x00000000 PIPEB_GMCH_DATA_N: 0x00000000 PIPEB_DP_LINK_M: 0x00000000 PIPEB_DP_LINK_N: 0x00000000 CURSOR_B_BASE: 0x00000000 CURSOR_B_CONTROL: 0x00000000 CURSOR_B_POSITION: 0x00000000 FPB0: 0x00021207 (n = 2, m1 = 18, m2 = 7) FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7) DPLL_B: 0x408b0000 (disabled, dvo, VGA, default clock, DAC/serial mode, p1 = 13, p2 = 4) DPLL_B_MD: 0x00000000 HTOTAL_B: 0x00000000 (1 active, 1 total) HBLANK_B: 0x00000000 (1 start, 1 end) HSYNC_B: 0x00000000 (1 start, 1 end) VTOTAL_B: 0x00000000 (1 active, 1 total) VBLANK_B: 0x00000000 (1 start, 1 end) VSYNC_B: 0x00000000 (1 start, 1 end) BCLRPAT_B: 0x00000000 VSYNCSHIFT_B: 0x00000000 VCLK_DIVISOR_VGA0: 0x00021207 VCLK_DIVISOR_VGA1: 0x00031406 VCLK_POST_DIV: 0x0000888b VGACNTRL: 0x8124008e (disabled) TV_CTL: 0x00000000 TV_DAC: 0x00000000 TV_CSC_Y: 0x00000000 TV_CSC_Y2: 0x00000000 TV_CSC_U: 0x00000000 TV_CSC_U2: 0x00000000 TV_CSC_V: 0x00000000 TV_CSC_V2: 0x00000000 TV_CLR_KNOBS: 0x00000000 TV_CLR_LEVEL: 0x00000000 TV_H_CTL_1: 0x00000000 TV_H_CTL_2: 0x00000000 TV_H_CTL_3: 0x00000000 TV_V_CTL_1: 0x00000000 TV_V_CTL_2: 0x00000000 TV_V_CTL_3: 0x00000000 TV_V_CTL_4: 0x00000000 TV_V_CTL_5: 0x00000000 TV_V_CTL_6: 0x00000000 TV_V_CTL_7: 0x00000000 TV_SC_CTL_1: 0x00000000 TV_SC_CTL_2: 0x00000000 TV_SC_CTL_3: 0x00000000 TV_WIN_POS: 0x00000000 TV_WIN_SIZE: 0x00000000 TV_FILTER_CTL_1: 0x00000000 TV_FILTER_CTL_2: 0x00000000 TV_FILTER_CTL_3: 0x00000000 TV_CC_CONTROL: 0x00000000 TV_CC_DATA: 0x00000000 TV_H_LUMA_0: 0x00000000 TV_H_LUMA_59: 0x00000000 TV_H_CHROMA_0: 0x00000000 TV_H_CHROMA_59: 0x00000000 FBC_CFB_BASE: 0x00000000 FBC_LL_BASE: 0x00000000 FBC_CONTROL: 0x00000000 FBC_COMMAND: 0x00000000 FBC_STATUS: 0x00000000 FBC_CONTROL2: 0x00000000 FBC_FENCE_OFF: 0x00000000 FBC_MOD_NUM: 0x00000000 MI_MODE: 0x00000000 MI_ARB_STATE: 0x00000000 MI_RDRET_STATE: 0x00000000 ECOSKPD: 0x00000307 DP_B: 0x00000000 DPB_AUX_CH_CTL: 0x00000000 DPB_AUX_CH_DATA1: 0x00000000 DPB_AUX_CH_DATA2: 0x00000000 DPB_AUX_CH_DATA3: 0x00000000 DPB_AUX_CH_DATA4: 0x00000000 DPB_AUX_CH_DATA5: 0x00000000 DP_C: 0x00000000 DPC_AUX_CH_CTL: 0x00000000 DPC_AUX_CH_DATA1: 0x00000000 DPC_AUX_CH_DATA2: 0x00000000 DPC_AUX_CH_DATA3: 0x00000000 DPC_AUX_CH_DATA4: 0x00000000 DPC_AUX_CH_DATA5: 0x00000000 DP_D: 0x00000000 DPD_AUX_CH_CTL: 0x00000000 DPD_AUX_CH_DATA1: 0x00000000 DPD_AUX_CH_DATA2: 0x00000000 DPD_AUX_CH_DATA3: 0x00000000 DPD_AUX_CH_DATA4: 0x00000000 DPD_AUX_CH_DATA5: 0x00000000 AUD_CONFIG: 0x00000000 AUD_HDMIW_STATUS: 0x00000000 AUD_CONV_CHCNT: 0x00000000 VIDEO_DIP_CTL: 0x00000000 AUD_PINW_CNTR: 0x00000000 AUD_CNTL_ST: 0x00000000 AUD_PIN_CAP: 0x00000000 AUD_PINW_CAP: 0x00000000 AUD_PINW_UNSOLRESP: 0x00000000 AUD_OUT_DIG_CNVT: 0x00000000 AUD_OUT_CWCAP: 0x00000000 AUD_GRP_CAP: 0x00000000 FENCE 0: 0x05000561 (enabled, X tiled, 32768 pitch, 0x05000000 - 0x07000000 (32768kb)) FENCE 1: 0x03800351 (enabled, X tiled, 16384 pitch, 0x03800000 - 0x04000000 (8192kb)) FENCE 2: 0x06000351 (enabled, X tiled, 16384 pitch, 0x06000000 - 0x06800000 (8192kb)) FENCE 3: 0x00000000 (disabled) FENCE 4: 0x02000561 (enabled, X tiled, 32768 pitch, 0x02000000 - 0x04000000 (32768kb)) FENCE 5: 0x00000000 (disabled) FENCE 6: 0x00600251 (enabled, X tiled, 16384 pitch, 0x00600000 - 0x00a00000 (4096kb)) FENCE 7: 0x00000000 (disabled) FENCE 8: 0x00000000 (disabled) FENCE 9: 0x00000000 (disabled) FENCE 10: 0x00000000 (disabled) FENCE 11: 0x00000000 (disabled) FENCE 12: 0x00000048 (disabled) FENCE 13: 0x00000002 (disabled) FENCE 14: 0x00000000 (disabled) FENCE 15: 0x00000000 (disabled) FENCE START 0: 0x00000000 (disabled) FENCE END 0: 0x00000000 (disabled) FENCE START 1: 0x00000000 (disabled) FENCE END 1: 0x00000000 (disabled) FENCE START 2: 0x00000048 (disabled) FENCE END 2: 0x00000002 (disabled) FENCE START 3: 0x00000000 (disabled) FENCE END 3: 0x00000000 (disabled) FENCE START 4: 0x00000000 (disabled) FENCE END 4: 0x00000000 (disabled) FENCE START 5: 0x00000000 (disabled) FENCE END 5: 0x00000000 (disabled) FENCE START 6: 0x00000000 (disabled) FENCE END 6: 0x00000000 (disabled) FENCE START 7: 0x00000000 (disabled) FENCE END 7: 0x00000000 (disabled) FENCE START 8: 0x00000000 (disabled) FENCE END 8: 0x00000000 (disabled) FENCE START 9: 0x00000000 (disabled) FENCE END 9: 0x00000000 (disabled) FENCE START 10: 0x00000000 (disabled) FENCE END 10: 0x00000000 (disabled) FENCE START 11: 0x00000000 (disabled) FENCE END 11: 0x00000000 (disabled) FENCE START 12: 0x00000000 (disabled) FENCE END 12: 0x00000000 (disabled) FENCE START 13: 0x00000000 (disabled) FENCE END 13: 0x00000000 (disabled) FENCE START 14: 0x00000000 (disabled) FENCE END 14: 0x00000000 (disabled) FENCE START 15: 0x00000000 (disabled) FENCE END 15: 0x00000000 (disabled) INST_PM: 0x00000000 pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4 pipe B dot 25153 n 2 m1 18 m2 7 p1 13 p2 4
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