On Tue, Jun 10, 2014 at 12:48:44PM +0530, sourab.gupta@xxxxxxxxx wrote: > From: Akash Goel <akash.goel@xxxxxxxxx> > > Removed the unconditional cross engine/ring update of MBOX registers. > The MBox update will done only when needed when the actual inter ring > dependency has been ascertained. Although this late sync could affect > the Media performance slightly but it shall improve the residency time > of individual power wells in C6 state. NAK. Did you even consider the deadlocks above and beyond the issues with latency? Maybe suggest that the hardware guys consider a reordering write FIFO next time like elsewhere on the chip. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
