From: Akash Goel <akash.goel@xxxxxxxxx>
Removed the unconditional cross engine/ring update of MBOX registers.
The MBox update will done only when needed when the actual inter ring
dependency has been ascertained. Although this late sync could affect
the Media performance slightly but it shall improve the residency time
of individual power wells in C6 state.
Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 ++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
2 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 279488a..c684b47 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -672,43 +672,35 @@ static void render_ring_cleanup(struct intel_engine_cs *ring)
}
static int gen6_signal(struct intel_engine_cs *signaller,
- unsigned int num_dwords)
+ struct intel_engine_cs *waiter,
+ u32 seqno)
{
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *useless;
- int i, ret;
+ u32 mbox_reg = signaller->semaphore.mbox.signal[waiter->id];
+ int ret;
/* NB: In order to be able to do semaphore MBOX updates for varying
* number of rings, it's easiest if we round up each individual update
* to a multiple of 2 (since ring updates must always be a multiple of
* 2) even though the actual update only requires 3 dwords.
*/
-#define MBOX_UPDATE_DWORDS 4
- if (i915_semaphore_is_enabled(dev))
- num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
- else
- return intel_ring_begin(signaller, num_dwords);
- ret = intel_ring_begin(signaller, num_dwords);
+#define MBOX_UPDATE_DWORDS 4
+ ret = intel_ring_begin(signaller, MBOX_UPDATE_DWORDS);
+#undef MBOX_UPDATE_DWORDS
if (ret)
return ret;
-#undef MBOX_UPDATE_DWORDS
-
- for_each_ring(useless, dev_priv, i) {
- u32 mbox_reg = signaller->semaphore.mbox.signal[i];
- if (mbox_reg != GEN6_NOSYNC) {
- intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(signaller, mbox_reg);
- intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
- intel_ring_emit(signaller, MI_NOOP);
- } else {
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_emit(signaller, MI_NOOP);
- intel_ring_emit(signaller, MI_NOOP);
- }
+ if (mbox_reg != GEN6_NOSYNC) {
+ intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit(signaller, mbox_reg);
+ intel_ring_emit(signaller, seqno);
+ intel_ring_emit(signaller, MI_NOOP);
+ } else {
+ intel_ring_emit(signaller, MI_NOOP);
+ intel_ring_emit(signaller, MI_NOOP);
+ intel_ring_emit(signaller, MI_NOOP);
+ intel_ring_emit(signaller, MI_NOOP);
}
+ __intel_ring_advance(signaller);
return 0;
}
@@ -727,7 +719,7 @@ gen6_add_request(struct intel_engine_cs *ring)
{
int ret;
- ret = ring->semaphore.signal(ring, 4);
+ ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
@@ -779,6 +771,13 @@ gen6_ring_sync(struct intel_engine_cs *waiter,
/* If seqno wrap happened, omit the wait with no-ops */
if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
+ /* Add the Mbox update command in the Signaller ring,
+ * this a point where the actual inter ring dependency has
+ * been ascertained.
+ */
+ ret = signaller->semaphore.signal(signaller, waiter, seqno+1);
+ if (ret)
+ return ret;
intel_ring_emit(waiter, dw1 | wait_mbox);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter, 0);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 910c83c..216c341 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -142,8 +142,8 @@ struct intel_engine_cs {
struct intel_engine_cs *to,
u32 seqno);
int (*signal)(struct intel_engine_cs *signaller,
- /* num_dwords needed by caller */
- unsigned int num_dwords);
+ struct intel_engine_cs *waiter,
+ u32 seqno);
} semaphore;
/**
--
1.8.5.1
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