Adds a function to enable and disable scrambling directly for the main link.
This is functionality required to establish more fine-grained control over
the Displayport interface, both for operational reliability and
compliance testing.
Signed-off-by: Todd Previte <tprevite@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c865c32..1209de8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2372,6 +2372,33 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
*DP = (*DP & ~mask) | signal_levels;
}
+void intel_dp_scrambler_disable(bool disable, struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ // SNB is 0x40000. ILK is 0x4400
+ // IVB is 0x64000, HSW+ is 0x64040/0x64140
+ uint32_t ctrl_reg, reg_value;
+
+ if (HAS_DDI(dev))
+ ctrl_reg = DP_TP_CTL(intel_dig_port->port);
+ else
+ ctrl_reg = intel_dp->output_reg;
+
+ reg_value = I915_READ(ctrl_reg);
+
+ // Scrambling is bit 7 (scrambling on == 0)
+ if (disable)
+ reg_value |= DP_TP_CTL_SCRAMBLE_DISABLE;
+ else
+ reg_value &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
+
+ I915_WRITE(ctrl_reg, reg_value);
+ POSTING_READ(ctrl_reg);
+}
+
bool
intel_dp_verify_link_status(DPLinkTrainingState state,
uint8_t lane_count,
--
1.8.3.2
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