Adds a function to check the link status across all lanes for Displayport.
This is functionality required to establish more fine-grained control over
the Displayport interface, both for operational reliability and
compliance testing.
Signed-off-by: Todd Previte <tprevite@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dp.c | 61 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 64c9803..c865c32 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -38,6 +38,22 @@
#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
+typedef enum {
+ LINK_TRAINING_STATUS_OK = 0,
+ LINK_TRAINING_CR_FAILED,
+ LINK_TRAINING_CR_COMPLETE,
+ LINK_TRAINING_CE_FAILED,
+ LINK_TRAINING_CE_COMPLETE,
+ LINK_TRAINING_STATUS_READ_FAILED
+} IntelDPLinkTrainingStatus;
+
+typedef enum {
+ DP_LINK_TRAINING_STATE_IDLE = 0,
+ DP_LINK_TRAINING_STATE_CLOCK_REC,
+ DP_LINK_TRAINING_STATE_CHANNEL_EQ,
+ DP_LINK_TRAINING_STATE_ADJUST
+} DPLinkTrainingState;
+
struct dp_link_dpll {
int link_bw;
struct dpll dpll;
@@ -2356,6 +2372,51 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
*DP = (*DP & ~mask) | signal_levels;
}
+bool
+intel_dp_verify_link_status(DPLinkTrainingState state,
+ uint8_t lane_count,
+ uint8_t *link_status)
+{
+ uint32_t status = 0;
+ bool link_ok = false;
+ uint8_t ls[5];
+
+ switch (state) {
+ case DP_LINK_TRAINING_STATE_CLOCK_REC:
+ status = (link_status[0] & DP_LANE_CR_DONE) +
+ ((link_status[0] >> 4) & DP_LANE_CR_DONE) +
+ (link_status[1] & DP_LANE_CR_DONE) +
+ ((link_status[1] >> 4) & DP_LANE_CR_DONE);
+ // Valid CR status = sum of bits == lane count
+ link_ok = status == lane_count ? true : false;
+ break;
+ case DP_LINK_TRAINING_STATE_CHANNEL_EQ:
+ ls[0] = ((link_status[0] & DP_LANE_CHANNEL_EQ_DONE) >> 1) +
+ ((link_status[0] & DP_LANE_SYMBOL_LOCKED) >> 2);
+ ls[1] = (((link_status[0] >> 4) & DP_LANE_CHANNEL_EQ_DONE) >> 1) +
+ (((link_status[0] >> 4) & DP_LANE_SYMBOL_LOCKED) >> 2);
+ ls[2] = ((link_status[1] & DP_LANE_CHANNEL_EQ_DONE) >> 1) +
+ ((link_status[1] & DP_LANE_SYMBOL_LOCKED) >> 2);
+ ls[3] = (((link_status[1] >> 4) & DP_LANE_CHANNEL_EQ_DONE) >> 1) +
+ (((link_status[1] >> 4) & DP_LANE_SYMBOL_LOCKED) >> 2);
+ ls[4] = link_status[2] & DP_INTERLANE_ALIGN_DONE;
+ // Combine lane status - must equal active lane count
+ status = ls[0] + ls[1] + ls[2] + ls[3];
+ // CE status is all lanes + lane alignment (ls[4])
+ link_ok = (status == lane_count) && ls[4] ? true : false;
+ break;
+ default:
+ // Invalid state for checking link status
+ break;
+ }
+
+ if (!link_ok) {
+ // FIXME: Log failure here, detailed error status output
+ }
+
+ return link_ok;
+}
+
uint32_t
intel_dp_set_training_pattern(uint8_t training_pattern,
struct intel_dp *intel_dp)
--
1.8.3.2
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