Hi Daniel, dear intel-experts, again I had the chance to test the latest intel-drm-nightly of the 3.14.0 kernel on the Siemens S6010 with its dreadful nso2501 DVO. Unfortunately, there are still a couple of issues here, and I also want to report on some progress and some workarounds. 1) Panning on the i830 still flickers, reproducible both on the Fujitsu S6010 and the IBM R31. The problem is all again the same, namely that the watermark is set too low (or too high, if you like). The intel_calculate_wm() function in intel_pm.c returns a watermark level of 0 for the nominal display configuration (1024x768), which is just too high. The maximum allowable watermark should be 8. I already submitted a patch for this problem, though unfortunately, it had not been accepted. Folks, could we *please* fix this issue? It is really trivial, and it really causes crashes if a video overlay is on the panning screen - thus, this is more than just a cosmetic fix. 2) Pipe_A quirk: Actually, this is not required or needed on the S6010 nor on the R31. In fact, it breaks more than it fixes. The problem is that the pipe A quirk causes the boot console to be misaligned with the screen, or to be completely blank. This is undesirable if you boot into maintenance mode (i.e. without an X interface). Just disabling the quirk avoids this problem in a wonderful way. 3) Suspend to RAM: Whether with or without the quirk, s2ram is non-functioning, but *almost* functioning. The problem on the S6010 is again the ns2501. Unfortunately, I do not know which of the intel functions are called on resume in which order, but it seems to me that the DVO is reprogrammed *before* the pipes and plls are reconfigured. Unfortunately, this cannot work with the ns2501. It requires proper PLL configuration for even receiving commands on the i2c bus, otherwise it locks up. Thus, it would be helpful to know which functions the intel driver runs through for resuming the display, maybe I would have then the chance to dig more into this. Everything else in the resume works, and one can an "almost working" resume by reprogramming the PLLs on resume by the intel-gpu-tools and calling a small script on resume: intel_reg_write 0x02120 0x0 intel_reg_write 0x61100 0x00000c00 intel_reg_write 0x61160 0x10004084 intel_reg_write 0x6101c 0x027f01df intel_reg_write 0x61000 0x031f027f intel_reg_write 0x61004 0x03170287 intel_reg_write 0x61008 0x02ef028f intel_reg_write 0x6100c 0x020c01df intel_reg_write 0x61010 0x020401e7 intel_reg_write 0x61014 0x01eb01e9 intel_reg_write 0x71180 0x01000000 intel_reg_write 0x70188 0x00001000 intel_reg_write 0x20d8 0x10E0108 intel_reg_write 0x20dc 0x102 intel_reg_write 0x61120 0x0 intel_reg_write 0x6014 0xD0820000 intel_reg_write 0x6018 0x0 intel_reg_write 0x61140 0x80004084 intel_reg_write 0x61160 0x90004084 This will give back a workable display, though with a couple of hick-ups. That is, on suspend, switch to the console (here also at 1024x768 resolution), then suspend. On resume, run the above script, then switch back to X. What is interesting is that the resume functionality seems to program the pipes differently. Resume tries to feed the display through pipe A, however, the DVO for the internal display is on pipe B. Here is the register dump before and after the resume: /* before */ DCC: 0x00000000 (0000ÿÿÿÿôÏ~·Zx·) CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present) C0DRB0: 0x00000000 (0x0000) C0DRB1: 0x00000000 (0x0000) C0DRB2: 0x00000000 (0x0000) C0DRB3: 0x00000000 (0x0000) C1DRB0: 0x00000000 (0x0000) C1DRB1: 0x00000000 (0x0000) C1DRB2: 0x00000000 (0x0000) C1DRB3: 0x00000000 (0x0000) C0DRA01: 0x00000000 (0x0000) C0DRA23: 0x00000000 (0x0000) C1DRA01: 0x00000000 (0x0000) C1DRA23: 0x00000000 (0x0000) PGETBL_CTL: 0x3ff60001 VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) CACHE_MODE_0: 0x00000000 D_STATE: 0x00000000 DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT) RENCLK_GATE_D1: 0x00000000 RENCLK_GATE_D2: 0x00000000 SDVOB: 0x80004084 (enabled, pipe A, stall disabled, detected) SDVOC: 0x90004084 (enabled, pipe A, stall disabled, detected) SDVOUDI: 0x00000000 DSPARB: 0x00017e5f DSPFW1: 0x00000000 DSPFW2: 0x00000000 DSPFW3: 0x00000000 ADPA: 0x00000c00 (disabled, pipe A, -hsync, -vsync) LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, -vsync) DVOC: 0x90004084 (enabled, pipe A, stall, -hsync, -vsync) DVOA_SRCDIM: 0x00000000 DVOB_SRCDIM: 0x00000000 DVOC_SRCDIM: 0x00000000 BLC_PWM_CTL: 0x00000000 BLC_PWM_CTL2: 0x00000000 PP_CONTROL: 0x00000000 (power target: off) PP_STATUS: 0x00000000 (off, not ready, sequencing idle) PP_ON_DELAYS: 0x00000000 PP_OFF_DELAYS: 0x00000000 PP_DIVISOR: 0x00000000 PFIT_CONTROL: 0x00000000 PFIT_PGM_RATIOS: 0x00000000 PORT_HOTPLUG_EN: 0x00000000 PORT_HOTPLUG_STAT: 0x00000000 DSPACNTR: 0x98000000 (enabled, pipe A) DSPASTRIDE: 0x00002000 (8192 bytes) DSPAPOS: 0x00000000 (0, 0) DSPASIZE: 0x02ff03ff (1024, 768) DSPABASE: 0x03000000 DSPASURF: 0x00000000 DSPATILEOFF: 0x00000000 PIPEACONF: 0x80000000 (enabled, single-wide) PIPEASRC: 0x03ff02ff (1024, 768) PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) PIPEA_GMCH_DATA_M: 0x00000000 PIPEA_GMCH_DATA_N: 0x00000000 PIPEA_DP_LINK_M: 0x00000000 PIPEA_DP_LINK_N: 0x00000000 CURSOR_A_BASE: 0x36b88000 CURSOR_A_CONTROL: 0x04000027 CURSOR_A_POSITION: 0x0090010b FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13) FPA1: 0x0004150d (n = 4, m1 = 21, m2 = 13) DPLL_A: 0xd0820000 (enabled, dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) DPLL_A_MD: 0x00000000 HTOTAL_A: 0x053f03ff (1024 active, 1344 total) HBLANK_A: 0x053f03ff (1024 start, 1344 end) HSYNC_A: 0x049f0417 (1048 start, 1184 end) VTOTAL_A: 0x032502ff (768 active, 806 total) VBLANK_A: 0x032502ff (768 start, 806 end) VSYNC_A: 0x03080302 (771 start, 777 end) BCLRPAT_A: 0x00000000 VSYNCSHIFT_A: 0x00000000 DSPBCNTR: 0x01000000 (disabled, pipe B) DSPBSTRIDE: 0x00000000 (0 bytes) DSPBPOS: 0x00000000 (0, 0) DSPBSIZE: 0x00000000 (1, 1) DSPBBASE: 0x00000000 DSPBSURF: 0x00000000 DSPBTILEOFF: 0x00000000 PIPEBCONF: 0x00000000 (disabled, single-wide) PIPEBSRC: 0x027f01df (640, 480) PIPEBSTAT: 0x10000000 (status: CRC_DONE_ENABLE) PIPEB_GMCH_DATA_M: 0x00000000 PIPEB_GMCH_DATA_N: 0x00000000 PIPEB_DP_LINK_M: 0x00000000 PIPEB_DP_LINK_N: 0x00000000 CURSOR_B_BASE: 0x00000000 CURSOR_B_CONTROL: 0x00000000 CURSOR_B_POSITION: 0x00000000 FPB0: 0x00021207 (n = 2, m1 = 18, m2 = 7) FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7) DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2) DPLL_B_MD: 0x00000000 HTOTAL_B: 0x031f027f (640 active, 800 total) HBLANK_B: 0x03170287 (648 start, 792 end) HSYNC_B: 0x02ef028f (656 start, 752 end) VTOTAL_B: 0x020c01df (480 active, 525 total) VBLANK_B: 0x020401e7 (488 start, 517 end) VSYNC_B: 0x01eb01e9 (490 start, 492 end) BCLRPAT_B: 0x00000000 VSYNCSHIFT_B: 0x00000000 VCLK_DIVISOR_VGA0: 0x00021207 VCLK_DIVISOR_VGA1: 0x00031406 VCLK_POST_DIV: 0x0000888b VGACNTRL: 0x80000000 (disabled) TV_CTL: 0x00000000 TV_DAC: 0x00000000 TV_CSC_Y: 0x00000000 TV_CSC_Y2: 0x00000000 TV_CSC_U: 0x00000000 TV_CSC_U2: 0x00000000 TV_CSC_V: 0x00000000 TV_CSC_V2: 0x00000000 TV_CLR_KNOBS: 0x00000000 TV_CLR_LEVEL: 0x00000000 TV_H_CTL_1: 0x00000000 TV_H_CTL_2: 0x00000000 TV_H_CTL_3: 0x00000000 TV_V_CTL_1: 0x00000000 TV_V_CTL_2: 0x00000000 TV_V_CTL_3: 0x00000000 TV_V_CTL_4: 0x00000000 TV_V_CTL_5: 0x00000000 TV_V_CTL_6: 0x00000000 TV_V_CTL_7: 0x00000000 TV_SC_CTL_1: 0x00000000 TV_SC_CTL_2: 0x00000000 TV_SC_CTL_3: 0x00000000 TV_WIN_POS: 0x00000000 TV_WIN_SIZE: 0x00000000 TV_FILTER_CTL_1: 0x00000000 TV_FILTER_CTL_2: 0x00000000 TV_FILTER_CTL_3: 0x00000000 TV_CC_CONTROL: 0x00000000 TV_CC_DATA: 0x00000000 TV_H_LUMA_0: 0x00000000 TV_H_LUMA_59: 0x00000000 TV_H_CHROMA_0: 0x00000000 TV_H_CHROMA_59: 0x00000000 FBC_CFB_BASE: 0x00000000 FBC_LL_BASE: 0x00000000 FBC_CONTROL: 0x00000000 FBC_COMMAND: 0x00000000 FBC_STATUS: 0x00000000 FBC_CONTROL2: 0x00000000 FBC_FENCE_OFF: 0x00000000 FBC_MOD_NUM: 0x00000000 MI_MODE: 0x00000000 MI_ARB_STATE: 0x00000000 MI_RDRET_STATE: 0x00000000 ECOSKPD: 0x00000307 DP_B: 0x00000000 DPB_AUX_CH_CTL: 0x00000000 DPB_AUX_CH_DATA1: 0x00000000 DPB_AUX_CH_DATA2: 0x00000000 DPB_AUX_CH_DATA3: 0x00000000 DPB_AUX_CH_DATA4: 0x00000000 DPB_AUX_CH_DATA5: 0x00000000 DP_C: 0x00000000 DPC_AUX_CH_CTL: 0x00000000 DPC_AUX_CH_DATA1: 0x00000000 DPC_AUX_CH_DATA2: 0x00000000 DPC_AUX_CH_DATA3: 0x00000000 DPC_AUX_CH_DATA4: 0x00000000 DPC_AUX_CH_DATA5: 0x00000000 DP_D: 0x00000000 DPD_AUX_CH_CTL: 0x00000000 DPD_AUX_CH_DATA1: 0x00000000 DPD_AUX_CH_DATA2: 0x00000000 DPD_AUX_CH_DATA3: 0x00000000 DPD_AUX_CH_DATA4: 0x00000000 DPD_AUX_CH_DATA5: 0x00000000 AUD_CONFIG: 0x00000000 AUD_HDMIW_STATUS: 0x00000000 AUD_CONV_CHCNT: 0x00000000 VIDEO_DIP_CTL: 0x00000000 AUD_PINW_CNTR: 0x00000000 AUD_CNTL_ST: 0x00000000 AUD_PIN_CAP: 0x00000000 AUD_PINW_CAP: 0x00000000 AUD_PINW_UNSOLRESP: 0x00000000 AUD_OUT_DIG_CNVT: 0x00000000 AUD_OUT_CWCAP: 0x00000000 AUD_GRP_CAP: 0x00000000 FENCE 0: 0x00400131 (enabled, X tiled, 4096 pitch, 0x00400000 - 0x00600000 (2048kb)) FENCE 1: 0x00000000 (disabled) FENCE 2: 0x01400351 (enabled, X tiled, 16384 pitch, 0x01400000 - 0x01c00000 (8192kb)) FENCE 3: 0x03000561 (enabled, X tiled, 32768 pitch, 0x03000000 - 0x05000000 (32768kb)) FENCE 4: 0x02000561 (enabled, X tiled, 32768 pitch, 0x02000000 - 0x04000000 (32768kb)) FENCE 5: 0x00000000 (disabled) FENCE 6: 0x00000000 (disabled) FENCE 7: 0x00000000 (disabled) FENCE 8: 0x00000000 (disabled) FENCE 9: 0x00000000 (disabled) FENCE 10: 0x00000000 (disabled) FENCE 11: 0x00000000 (disabled) FENCE 12: 0x00000048 (disabled) FENCE 13: 0x00000002 (disabled) FENCE 14: 0x00000000 (disabled) FENCE 15: 0x00000000 (disabled) FENCE START 0: 0x00000000 (disabled) FENCE END 0: 0x00000000 (disabled) FENCE START 1: 0x00000000 (disabled) FENCE END 1: 0x00000000 (disabled) FENCE START 2: 0x00000048 (disabled) FENCE END 2: 0x00000002 (disabled) FENCE START 3: 0x00000000 (disabled) FENCE END 3: 0x00000000 (disabled) FENCE START 4: 0x00000000 (disabled) FENCE END 4: 0x00000000 (disabled) FENCE START 5: 0x00000000 (disabled) FENCE END 5: 0x00000000 (disabled) FENCE START 6: 0x00000000 (disabled) FENCE END 6: 0x00000000 (disabled) FENCE START 7: 0x00000000 (disabled) FENCE END 7: 0x00000000 (disabled) FENCE START 8: 0x00000000 (disabled) FENCE END 8: 0x00000000 (disabled) FENCE START 9: 0x00000000 (disabled) FENCE END 9: 0x00000000 (disabled) FENCE START 10: 0x00000000 (disabled) FENCE END 10: 0x00000000 (disabled) FENCE START 11: 0x00000000 (disabled) FENCE END 11: 0x00000000 (disabled) FENCE START 12: 0x00000000 (disabled) FENCE END 12: 0x00000000 (disabled) FENCE START 13: 0x00000000 (disabled) FENCE END 13: 0x00000000 (disabled) FENCE START 14: 0x00000000 (disabled) FENCE END 14: 0x00000000 (disabled) FENCE START 15: 0x00000000 (disabled) FENCE END 15: 0x00000000 (disabled) INST_PM: 0x00000000 pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4 pipe B dot 327000 n 2 m1 18 m2 7 p1 2 p2 2 /* and after */ DCC: 0x00000000 (0000ÿÿÿÿô|·Z³u·) CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present) C0DRB0: 0x00000000 (0x0000) C0DRB1: 0x00000000 (0x0000) C0DRB2: 0x00000000 (0x0000) C0DRB3: 0x00000000 (0x0000) C1DRB0: 0x00000000 (0x0000) C1DRB1: 0x00000000 (0x0000) C1DRB2: 0x00000000 (0x0000) C1DRB3: 0x00000000 (0x0000) C0DRA01: 0x00000000 (0x0000) C0DRA23: 0x00000000 (0x0000) C1DRA01: 0x00000000 (0x0000) C1DRA23: 0x00000000 (0x0000) PGETBL_CTL: 0x3ff60001 VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7) VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6) VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4) DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled) CACHE_MODE_0: 0x001f0000 D_STATE: 0x00000000 DSPCLK_GATE_D: 0x00000008 (clock gates disabled: OVRUNIT) RENCLK_GATE_D1: 0x00000000 RENCLK_GATE_D2: 0x00000000 SDVOB: 0x80004084 (enabled, pipe A, stall disabled, detected) SDVOC: 0x90004084 (enabled, pipe A, stall disabled, detected) SDVOUDI: 0x00000000 DSPARB: 0x00017e5f DSPFW1: 0x00000000 DSPFW2: 0x00000000 DSPFW3: 0x00000000 ADPA: 0x00000000 (disabled, pipe A, -hsync, -vsync) LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel) DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) DVOB: 0x80004084 (enabled, pipe A, no stall, -hsync, -vsync) DVOC: 0x90004084 (enabled, pipe A, stall, -hsync, -vsync) DVOA_SRCDIM: 0x00000000 DVOB_SRCDIM: 0x00000000 DVOC_SRCDIM: 0x00000000 BLC_PWM_CTL: 0x00000000 BLC_PWM_CTL2: 0x00000000 PP_CONTROL: 0x00000000 (power target: off) PP_STATUS: 0x00000000 (off, not ready, sequencing idle) PP_ON_DELAYS: 0x00000000 PP_OFF_DELAYS: 0x00000000 PP_DIVISOR: 0x00000000 PFIT_CONTROL: 0x00000000 PFIT_PGM_RATIOS: 0x00000000 PORT_HOTPLUG_EN: 0x00000000 PORT_HOTPLUG_STAT: 0x00000000 DSPACNTR: 0x98000000 (enabled, pipe A) DSPASTRIDE: 0x00002000 (8192 bytes) DSPAPOS: 0x00000000 (0, 0) DSPASIZE: 0x02ff03ff (1024, 768) DSPABASE: 0x03000000 DSPASURF: 0x00000000 DSPATILEOFF: 0x00000000 PIPEACONF: 0x80000000 (enabled, single-wide) PIPEASRC: 0x03ff02ff (1024, 768) PIPEASTAT: 0x10000207 (status: CRC_DONE_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS) PIPEA_GMCH_DATA_M: 0x00000000 PIPEA_GMCH_DATA_N: 0x00000000 PIPEA_DP_LINK_M: 0x00000000 PIPEA_DP_LINK_N: 0x00000000 CURSOR_A_BASE: 0x36b88000 CURSOR_A_CONTROL: 0x04000027 CURSOR_A_POSITION: 0x00040007 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13) FPA1: 0x0004150d (n = 4, m1 = 21, m2 = 13) DPLL_A: 0xd0820000 (enabled, dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4) DPLL_A_MD: 0x00000000 HTOTAL_A: 0x053f03ff (1024 active, 1344 total) HBLANK_A: 0x053f03ff (1024 start, 1344 end) HSYNC_A: 0x049f0417 (1048 start, 1184 end) VTOTAL_A: 0x032502ff (768 active, 806 total) VBLANK_A: 0x032502ff (768 start, 806 end) VSYNC_A: 0x03080302 (771 start, 777 end) BCLRPAT_A: 0x00000000 VSYNCSHIFT_A: 0x00000000 DSPBCNTR: 0x00000000 (disabled, pipe A) DSPBSTRIDE: 0x00000000 (0 bytes) DSPBPOS: 0x00000000 (0, 0) DSPBSIZE: 0x00000000 (1, 1) DSPBBASE: 0x00000000 DSPBSURF: 0x00000000 DSPBTILEOFF: 0x00000000 PIPEBCONF: 0x00000000 (disabled, single-wide) PIPEBSRC: 0x00000000 (1, 1) PIPEBSTAT: 0x10000004 (status: CRC_DONE_ENABLE SVBLANK_INT_STATUS) PIPEB_GMCH_DATA_M: 0x00000000 PIPEB_GMCH_DATA_N: 0x00000000 PIPEB_DP_LINK_M: 0x00000000 PIPEB_DP_LINK_N: 0x00000000 CURSOR_B_BASE: 0x00000000 CURSOR_B_CONTROL: 0x00000000 CURSOR_B_POSITION: 0x00000000 FPB0: 0x00021207 (n = 2, m1 = 18, m2 = 7) FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7) DPLL_B: 0x00000000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 2) DPLL_B_MD: 0x00000000 HTOTAL_B: 0x00000000 (1 active, 1 total) HBLANK_B: 0x00000000 (1 start, 1 end) HSYNC_B: 0x00000000 (1 start, 1 end) VTOTAL_B: 0x00000000 (1 active, 1 total) VBLANK_B: 0x00000000 (1 start, 1 end) VSYNC_B: 0x00000000 (1 start, 1 end) BCLRPAT_B: 0x00000000 VSYNCSHIFT_B: 0x00000000 VCLK_DIVISOR_VGA0: 0x00021207 VCLK_DIVISOR_VGA1: 0x00031406 VCLK_POST_DIV: 0x0000888b VGACNTRL: 0x80000000 (disabled) TV_CTL: 0x00000000 TV_DAC: 0x00000000 TV_CSC_Y: 0x00000000 TV_CSC_Y2: 0x00000000 TV_CSC_U: 0x00000000 TV_CSC_U2: 0x00000000 TV_CSC_V: 0x00000000 TV_CSC_V2: 0x00000000 TV_CLR_KNOBS: 0x00000000 TV_CLR_LEVEL: 0x00000000 TV_H_CTL_1: 0x00000000 TV_H_CTL_2: 0x00000000 TV_H_CTL_3: 0x00000000 TV_V_CTL_1: 0x00000000 TV_V_CTL_2: 0x00000000 TV_V_CTL_3: 0x00000000 TV_V_CTL_4: 0x00000000 TV_V_CTL_5: 0x00000000 TV_V_CTL_6: 0x00000000 TV_V_CTL_7: 0x00000000 TV_SC_CTL_1: 0x00000000 TV_SC_CTL_2: 0x00000000 TV_SC_CTL_3: 0x00000000 TV_WIN_POS: 0x00000000 TV_WIN_SIZE: 0x00000000 TV_FILTER_CTL_1: 0x00000000 TV_FILTER_CTL_2: 0x00000000 TV_FILTER_CTL_3: 0x00000000 TV_CC_CONTROL: 0x00000000 TV_CC_DATA: 0x00000000 TV_H_LUMA_0: 0x00000000 TV_H_LUMA_59: 0x00000000 TV_H_CHROMA_0: 0x00000000 TV_H_CHROMA_59: 0x00000000 FBC_CFB_BASE: 0x00000000 FBC_LL_BASE: 0x00000000 FBC_CONTROL: 0x00000000 FBC_COMMAND: 0x00000000 FBC_STATUS: 0x00000000 FBC_CONTROL2: 0x00000000 FBC_FENCE_OFF: 0x00000000 FBC_MOD_NUM: 0x00000000 MI_MODE: 0x00000000 MI_ARB_STATE: 0x00000000 MI_RDRET_STATE: 0x00000000 ECOSKPD: 0x00000307 DP_B: 0x00000000 DPB_AUX_CH_CTL: 0x00000000 DPB_AUX_CH_DATA1: 0x00000000 DPB_AUX_CH_DATA2: 0x00000000 DPB_AUX_CH_DATA3: 0x00000000 DPB_AUX_CH_DATA4: 0x00000000 DPB_AUX_CH_DATA5: 0x00000000 DP_C: 0x00000000 DPC_AUX_CH_CTL: 0x00000000 DPC_AUX_CH_DATA1: 0x00000000 DPC_AUX_CH_DATA2: 0x00000000 DPC_AUX_CH_DATA3: 0x00000000 DPC_AUX_CH_DATA4: 0x00000000 DPC_AUX_CH_DATA5: 0x00000000 DP_D: 0x00000000 DPD_AUX_CH_CTL: 0x00000000 DPD_AUX_CH_DATA1: 0x00000000 DPD_AUX_CH_DATA2: 0x00000000 DPD_AUX_CH_DATA3: 0x00000000 DPD_AUX_CH_DATA4: 0x00000000 DPD_AUX_CH_DATA5: 0x00000000 AUD_CONFIG: 0x00000000 AUD_HDMIW_STATUS: 0x00000000 AUD_CONV_CHCNT: 0x00000000 VIDEO_DIP_CTL: 0x00000000 AUD_PINW_CNTR: 0x00000000 AUD_CNTL_ST: 0x00000000 AUD_PIN_CAP: 0x00000000 AUD_PINW_CAP: 0x00000000 AUD_PINW_UNSOLRESP: 0x00000000 AUD_OUT_DIG_CNVT: 0x00000000 AUD_OUT_CWCAP: 0x00000000 AUD_GRP_CAP: 0x00000000 FENCE 0: 0x00400131 (enabled, X tiled, 4096 pitch, 0x00400000 - 0x00600000 (2048kb)) FENCE 1: 0x00000000 (disabled) FENCE 2: 0x01400351 (enabled, X tiled, 16384 pitch, 0x01400000 - 0x01c00000 (8192kb)) FENCE 3: 0x03000561 (enabled, X tiled, 32768 pitch, 0x03000000 - 0x05000000 (32768kb)) FENCE 4: 0x02000561 (enabled, X tiled, 32768 pitch, 0x02000000 - 0x04000000 (32768kb)) FENCE 5: 0x00000000 (disabled) FENCE 6: 0x00000000 (disabled) FENCE 7: 0x00000000 (disabled) FENCE 8: 0x00000000 (disabled) FENCE 9: 0x00000000 (disabled) FENCE 10: 0x00000000 (disabled) FENCE 11: 0x00000000 (disabled) FENCE 12: 0x00000048 (disabled) FENCE 13: 0x00000002 (disabled) FENCE 14: 0x00000000 (disabled) FENCE 15: 0x00000000 (disabled) FENCE START 0: 0x00000000 (disabled) FENCE END 0: 0x00000000 (disabled) FENCE START 1: 0x00000000 (disabled) FENCE END 1: 0x00000000 (disabled) FENCE START 2: 0x00000048 (disabled) FENCE END 2: 0x00000002 (disabled) FENCE START 3: 0x00000000 (disabled) FENCE END 3: 0x00000000 (disabled) FENCE START 4: 0x00000000 (disabled) FENCE END 4: 0x00000000 (disabled) FENCE START 5: 0x00000000 (disabled) FENCE END 5: 0x00000000 (disabled) FENCE START 6: 0x00000000 (disabled) FENCE END 6: 0x00000000 (disabled) FENCE START 7: 0x00000000 (disabled) FENCE END 7: 0x00000000 (disabled) FENCE START 8: 0x00000000 (disabled) FENCE END 8: 0x00000000 (disabled) FENCE START 9: 0x00000000 (disabled) FENCE END 9: 0x00000000 (disabled) FENCE START 10: 0x00000000 (disabled) FENCE END 10: 0x00000000 (disabled) FENCE START 11: 0x00000000 (disabled) FENCE END 11: 0x00000000 (disabled) FENCE START 12: 0x00000000 (disabled) FENCE END 12: 0x00000000 (disabled) FENCE START 13: 0x00000000 (disabled) FENCE END 13: 0x00000000 (disabled) FENCE START 14: 0x00000000 (disabled) FENCE END 14: 0x00000000 (disabled) FENCE START 15: 0x00000000 (disabled) FENCE END 15: 0x00000000 (disabled) INST_PM: 0x00000000 pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4 pipe B dot 327000 n 2 m1 18 m2 7 p1 2 p2 2 Note that this is already with the pipe A quirk removed. Apparently, something is wrong in the driver when trying to re-establishing the display. Everything else works on resume, i.e. sound, wifi, mouse,... are all in good shape. Note that post-ing the display through the bios (i.e. vbetool post) is *not* a good idea as it leaves the GPU in a useless state. Also, setting the vbemode through the bios (i.e. vbetool vbemode set 16664) does not work as desired. That is, the usual candidates for establishing the display have been tried and are non-working. Hope this helps for narrowing the problem. Thanks, Thomas _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx