On Wed, Mar 26, 2014 at 06:41:51PM +0000, Damien Lespiau wrote:
> Not implementing this W/A can lead to hangs.
>
> Cc: Ben Widawsky <benjamin.widawsky@xxxxxxxxx>
> Cc: Rafael Barbalho <rafael.barbalho@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
>From reading the HSD, it's not a workaround. It was a spec bug. I
presume the workaround name came from the workaround database? If it did
not, I'd just drop any mention of "workaround." If it's in the
workaround database, maybe just leave it so we can check later.
Either way:
Reviewed-by: Ben Widawsky <ben@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0ebc20d..927a7c1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1060,7 +1060,8 @@ enum punit_power_well {
> #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
> #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
> #define CACHE_MODE_1 0x7004 /* IVB+ */
> -#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
> +#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
> +#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
>
> #define GEN6_BLITTER_ECOSKPD 0x221d0
> #define GEN6_BLITTER_LOCK_SHIFT 16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c1e2d75..b66a43b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4882,6 +4882,10 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> /* WaDisableSDEUnitClockGating:bdw */
> I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +
> + /* Wa4x4STCOptimizationDisable:bdw */
> + I915_WRITE(CACHE_MODE_1,
> + _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
> }
>
> static void haswell_init_clock_gating(struct drm_device *dev)
> --
> 1.8.3.1
>
--
Ben Widawsky, Intel Open Source Technology Center
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