On Mon, Mar 24, 2014 at 12:19:24PM +0530, sourab.gupta@xxxxxxxxx wrote: > From: Akash Goel <akash.goel@xxxxxxxxx> > > For VLV, disabling L3 clock gating- MMIO 940c[25] = 1 > > Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx> > Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_pm.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6c04b79..fbfdca7 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5096,8 +5096,11 @@ static void valleyview_init_clock_gating(struct drm_device *dev) > I915_WRITE(GEN6_UCGCTL2, > GEN6_RCZUNIT_CLOCK_GATE_DISABLE); > > - /* WaDisableL3Bank2xClockGate:vlv */ > - I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); > + /* WaDisableL3Bank2xClockGate:vlv > + * Disabling L3 clock gating- MMIO 940c[25] = 1 > + * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ Who's the intended audience for this comment? It doesn't provide the reader with any more information than the following line. And this patch only converts the write into a rmw, so the entire patch is misleading. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/intel-gfx
