On Mon, Mar 24, 2014 at 12:19:23PM +0530, sourab.gupta@xxxxxxxxx wrote:
> From: Akash Goel <akash.goel@xxxxxxxxx>
>
> In Valleyview, Operational flush cannot be enabled on
> BWG A0 [Errata BWT006]
>
> Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
> Signed-off-by: Sourab Gupta <sourab.gupta@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fd25e8e4..803f392 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -974,6 +974,9 @@ enum punit_power_well {
> #define ECO_GATING_CX_ONLY (1<<3)
> #define ECO_FLIP_DONE (1<<0)
>
> +#define GEN7_CACHE_MODE_0 0x07000 /* IVB+ only */
> +#define GEN7_RC_OP_FLUSH_ENABLE (1<<0)
> +
> #define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
> #define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
> #define CACHE_MODE_1 0x7004 /* IVB+ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index fd68f93..6c04b79 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5068,6 +5068,12 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
>
> + /* WaDisable_RenderCache_OperationalFlush:vlv
> + * Clear bit 0, so we do a AND with the mask
> + * to keep other bits the same */
> + I915_WRITE(GEN7_CACHE_MODE_0, (I915_READ(GEN7_CACHE_MODE_0) |
> + _MASKED_BIT_DISABLE(GEN7_RC_OP_FLUSH_ENABLE)));
It's a masked register, so why the read...
Bonus points for a nonsense comment.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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