On Fri, Feb 07, 2014 at 05:52:10PM +0530, akash.goel@xxxxxxxxx wrote:
> From: Akash Goel <akash.goel@xxxxxxxxx>
>
> Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
> In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
> Store data commands.
>
> v2: Modified the WA comment. (Ville)
>
> Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d897a19..2ac6600 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2183,6 +2183,29 @@ intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
> uint32_t flush_domains;
> int ret;
>
> + if (IS_VALLEYVIEW(ring->dev)) {
> + /*
> + * WaTlbInvalidateStoreDataBefore
> + * Before pipecontrol with TLB invalidate set, need 2 store
> + * data commands (such as MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX)
> + * Without this, hardware cannot guarantee the command after the
> + * PIPE_CONTROL with TLB inv will not use the old TLB values.
> + * FIXME, should also apply to snb, ivb
> + */
We have a small syntax to indicate for which platform a W/A has been
implemented so a script in intel-gpu-tool can pick them up and make a
list. It's a bit low-fi, but has proven to be handy to quickly check
what we implement for a specific platform.
So this should be WaTlbInvalidateStoreDataBefore:vlv
This script works like this:
$ /path/to/intel-gpu-tools/scripts/list-workarounds -p vlv /path/to/kernel
WaCatErrorRejectionIssue
WaDisableAsyncFlipPerfMode
WaDisableBackToBackFlipFix
WaDisableDopClockGating
WaDisableEarlyCull
WaDisableL3Bank2xClockGate
WaDisablePSDDualDispatchEnable
...
--
Damien
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