From: Akash Goel <akash.goel@xxxxxxxxx>
Added a new rendering specific Workaround 'WaReadAfterWriteHazard'.
In this WA, need to add 12 MI Store Dword commands to ensure proper
flush of h/w pipeline.
v2: Modified the WA comment (Ville)
Signed-off-by: Akash Goel <akash.goel@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2ac6600..49370a1 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2173,6 +2173,32 @@ intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
+ if (IS_VALLEYVIEW(ring->dev)) {
+ /*
+ * WaReadAfterWriteHazard
+ * Send a number of Store Data commands here to finish
+ * flushing hardware pipeline.This is needed in the case
+ * where the next workload tries reading from the same
+ * surface that this batch writes to. Without these StoreDWs,
+ * not all of the data will actually be flushd to the surface
+ * by the time the next batch starts reading it, possibly
+ * causing a small amount of corruption.
+ * FIXME, should also apply to snb, ivb.
+ */
+ int i;
+ ret = intel_ring_begin(ring, 4 * 12);
+ if (ret)
+ return ret;
+ for (i = 0; i < 12; i++) {
+ intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
+ intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX <<
+ MI_STORE_DWORD_INDEX_SHIFT);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, MI_NOOP);
+ }
+ intel_ring_advance(ring);
+ }
+
ring->gpu_caches_dirty = false;
return 0;
}
--
1.8.5.2
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